diff --git a/book/.gitignore b/book/.gitignore new file mode 100644 index 0000000..eca3603 --- /dev/null +++ b/book/.gitignore @@ -0,0 +1,19 @@ +book.aux +book.brf +book.idx +book.ilg +book.ind +book.lof +book.log +book.pdf +book.toc +book.bbl +book.blg +book.out +*.aux +book.glg +book.glo +book.gls +book.glsdefs +book.ist +*.bak diff --git a/book/Makefile b/book/Makefile new file mode 100644 index 0000000..cd39769 --- /dev/null +++ b/book/Makefile @@ -0,0 +1,17 @@ +TOP=.. +include $(TOP)/Make.rules + +TEXPATH=./numbers:./intro:./rv32:./copyright:./license + +SUBDIRS= + +all:: book.pdf + +clean:: + rm -f book.pdf */*.aux $(LATEX_CLEANFILES) + +book.pdf:: *.tex bibliography.bib + +spell: + #find . -name "*.tex" -exec aspell --lang=en --mode=tex check "{}" \; + find . -name "*.tex" -exec aspell --mode=tex check "{}" \; diff --git a/book/bibliography.bib b/book/bibliography.bib new file mode 100644 index 0000000..b62190c --- /dev/null +++ b/book/bibliography.bib @@ -0,0 +1,147 @@ +@string{IETF="Internet Engineering Task Force"} + +@manual{rvismv1v22:2017, + title = "\href{https://github.com/riscv/riscv-isa-manual}{The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 2.2}", + organization = "\href{https://riscv.org/}{RISC-V Foundation}", + year = 2017, + month = 5, + note = {Editors Andrew Waterman and Krste Asanovi\'c} +} + +The RISC-V Instruction Set Manual +Volume II: Privileged Architecture +@manual{rvismv2:2017, + title = "\href{https://github.com/riscv/riscv-isa-manual}{The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Document Version 1.10}", + organization = "\href{https://riscv.org/}{RISC-V Foundation}", + year = 2017, + month = 5, + note = {Editors Andrew Waterman and Krste Asanovi\'c} +} + +@book{riscvreader:2017, + title = {The RISC-V Reader: An Open Architecture Atlas}, + author = {David Patterson and Andrew Waterman}, + publisher = {Strawberry Canyon}, + month = 11, + year = 2017, + note = {ISBN: 978-0999249116} +} + +@book{codriscv:2017, + title = {Computer Organization and Design RISC-V Edition: The Hardware Software Interface}, + author = {David Patterson and John Hennessy}, + publisher = {Morgan Kaufmann}, + month = 4, + year = 2017, + note = {ISBN: 978-0128122754} + + +@book{gcc:2017, + title = "\href{https://gcc.gnu.org/onlinedocs/}{Using the GNU Compiler Collection (For GCC version 7.3.0)}", + author = {Richard M. Stallman and the GCC Developer Community}, + publisher = {GNU Press}, + address = {Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA}, + year = 2017 +} + + +@article{Decker:1985:MAT:989369.989375, + author = {Decker, William F.}, + title = {A Modern Approach to Teaching Computer Organization and Assembly Language Programming}, + journal = {SIGCSE Bull.}, + issue_date = {December 1985}, + volume = {17}, + number = {4}, + month = 12, + year = {1985}, + issn = {0097-8418}, + pages = {38--44}, + numpages = {7}, + url = {http://doi.acm.org/10.1145/989369.989375}, + doi = {10.1145/989369.989375}, + acmid = {989375}, + publisher = {ACM}, + address = {New York, NY, USA} +} + + +@manual{mcs85:1978, + title = {MCS-85 User's Manual}, + organization = {Intel}, + month = 9, + year = 1978 +} + +@manual{edtasm:1978, + title = {TRS-80 Editor/Assembler Operation and Reference Manual}, + organization = {Radio Shack}, + year = 1978 +} + +@manual{mc68000:1980, + title = {MC68000 16--bit Microprocessor User's Manual}, + edition = {2nd}, + organization = {Motorola}, + month = 1, + year = 1980, + note = {MC68000UM(AD2)} +} +@manual{ns32k:1986, + title = {Series 32000 Databook}, + organization = {National Semiconductor Coprporation}, + year = 1986 +} + +@book{assist:1983, + title = {Assembler Language With ASSIST}, + author = {Ross A. Overbeek and W. E. Singletary}, + edition = {2nd}, + publisher = {Science Research Associates, Inc.}, + year = 1983 +} + +@manual{poo:1980, + title = {IBM System/370 Principals of Operation}, + edition = {7th}, + organization = {IBM}, + month = 3, + year = 1980 +} + +@manual{assembler370:1979, + title = {OS/VS-DOS/VSE-VM/370 Assembler Language}, + edition = {6th}, + organization = {IBM}, + month = 3, + year = 1979 +} + + +@manual{ttl74154:1979, + title = "\href{http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sdls056&fileType=pdf}{SN54154, SN74154 4--line to 16--line Decoders/Demultiplexers}", + organization = {Texas Instruments}, + month = 12, + year = 1972 +} + +@manual{ttl74191:1979, + title = "\href{http://www.ti.com/lit/ds/symlink/sn74ls191.pdf}{SN54190, SN54191, SN54LS190, SN54LS191, SN74190, SN74191, SN74LS190, SN74LS191 Synchronous Up/Down Counters With Down/Up Mode Control}", + organization = {Texas Instruments}, + month = 3, + year = 1988 +} + + + +@Misc{IEN137, + author = "Danny Cohen", + title = "\href{http://www.ietf.org/rfc/ien/ien137.txt}{IEN 137, On Holy Wars and a Plea for Peace}", + month = apr, + year = "1980", + note = "This note discusses the Big-Endian/Little-Endian + byte/bit-order controversy, but did not settle it. A + decade later, David V. James in ``Multiplexed Buses: + The Endian Wars Continue'', {\em IEEE Micro}, {\bf + 10}(3), 9--21 (1990) continued the discussion.", +%%% URL = "http://www.ietf.org/rfc/ien/ien137.txt", +} diff --git a/book/book.tex b/book/book.tex new file mode 100644 index 0000000..c5feafc --- /dev/null +++ b/book/book.tex @@ -0,0 +1,95 @@ +%\documentclass[oneside,draft,letterpaper]{book} +%\documentclass[letterpaper]{book} +\documentclass[oneside,letterpaper]{book} + +\input{preamble} +\input{colors} +\input{insnformats} + +\usepackage{ENote} + +%\usepackage{showframe} + +\hypersetup{ + pdfauthor={John Winans}, + pdftitle={RISC-V Assembly Language Programming (Draft \GitRevision{})}, + pdfkeywords={RISC-V} {Assembler} +} + +\makeindex + +%\makeglossaries +\makenoidxglossaries +\include{glossary} + +\begin{document} +\include{indexrefs} % The see-references for the index + + +% Why does this (apparently) have to go here???? +\newlength{\fullwidth} +\setlength{\fullwidth}{\the\textwidth} +\addtolength{\fullwidth}{\the\marginparsep} +\addtolength{\fullwidth}{\the\marginparwidth} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\frontmatter + +\title{RISC-V\\Assembly Language Programming\\{\normalsize (Draft \GitRevision{})}} +\author{John Winans\\ \href{mailto:jwinans@niu.edu}{\sf jwinans@niu.edu}} +%\date{May } + +\maketitle + +\include{copyright/chapter} +\tableofcontents +%\listoffigures + +\setlength{\parskip}{10pt} + +\include{preface/chapter} +\mainmatter + +%\include{preface/chapter} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +% there should be one include here for each chapter + +%\part{Introduction} + +%\include{intro/chapter} +\include{numbers/chapter} +\include{toolchain/chapter} +\include{rv32/chapter} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% These 'chapters' are lettered rather than numbered + +\appendix +\include{license/chapter} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\backmatter +% putting a chapter here causes it to be unnumbered + + +\clearpage +\bibliography{bibliography} +\addcontentsline{toc}{chapter}{Bibliography} +%\nocite{*} % force all bib items to file appear even if not cited +%\bibliographystyle{alpha} +\bibliographystyle{ieeetr} + +\clearpage +\phantomsection +\addcontentsline{toc}{chapter}{\indexname} +\printindex + +%\clearpage +%\phantomsection +\glsaddall +\printnoidxglossaries +%\printglossary + +\end{document} diff --git a/book/colors.tex b/book/colors.tex new file mode 100644 index 0000000..7775bdc --- /dev/null +++ b/book/colors.tex @@ -0,0 +1,5 @@ +% These are color styles used in the figures in this book. +\definecolor{c_lightblue}{HTML}{B0E0FF} +\definecolor{c_lightred}{HTML}{FFE0E0} +\definecolor{c_lightyellow}{HTML}{FFE060} +\definecolor{c_lightgreen}{HTML}{C0FFC0} diff --git a/book/copyright/chapter.tex b/book/copyright/chapter.tex new file mode 100644 index 0000000..57ea27e --- /dev/null +++ b/book/copyright/chapter.tex @@ -0,0 +1,13 @@ +\thispagestyle{plain} + +Copyright \copyright\ 2018 John Winans + +This document is made available under a Creative Commons Attribution 4.0 +International License. See \autoref{license} for more information. + +Download your own copy of this book from github here: +\url{https://github.com/johnwinans/rvalp}. + +This document may contain inaccuracies or errors. The author provides no +guarantee regarding the accuracy of this document's contents. If you +discover that this document contains errors, please notify the author. diff --git a/book/glossary.tex b/book/glossary.tex new file mode 100644 index 0000000..0f84a89 --- /dev/null +++ b/book/glossary.tex @@ -0,0 +1,93 @@ +\newglossaryentry{latex} +{ + name=LaTeX, + description={Is a mark up language specially suited + for scientific documents} +} + +\newglossaryentry{bit} +{ + name=bit, + description={One binary digit} +} +\newglossaryentry{hit} +{ + name={hit}, + description={One hex digit} +} +\newglossaryentry{byte} +{ + name=byte, + description={A binary value represented by 8 bits} +} +\newglossaryentry{HalfWord} +{ + name={Halfword}, + description={A binary value represented by 16 bits} +} +\newglossaryentry{FullWord} +{ + name={Fullword}, + description={A binary value represented by 32 bits} +} +\newglossaryentry{DoubleWord} +{ + name={Doubleword}, + description={A binary value represented by 64 bits} +} +\newglossaryentry{QuadWord} +{ + name={Quadword}, + description={A binary value represented by 128 bits} +} +\newglossaryentry{HighOrderBits} +{ + name={High order bits}, + description={Some number of MSBs} +} +\newglossaryentry{LowOrderBits} +{ + name={Low order bits}, + description={Some number of LSBs} +} + +\newglossaryentry{xlen} +{ + name=XLEN, + description={The number of bits a RISC-V x integer register + (such as x0). For RV32 XLEN=32, RV64 XLEN=64 etc} +} +\newglossaryentry{rv32} +{ + name=RV32, + description={Short for RISC-V 32. The number 32 refers to the XLEN} +} +\newglossaryentry{rv64} +{ + name=RV64, + description={Short for RISC-V 64. The number 64 refers to the XLEN} +} +\newglossaryentry{overflow} +{ + name=overflow, + description={The situation where the result of an addition or + subtraction operation is approaching positive or negative + infinity and exceeds the number of bits alloted to contain + the result. This is typically caused by high--order truncation} +} +\newglossaryentry{underflow} +{ + name=underflow, + description={The situation where the result of an addition or + subtraction operation is approaching zero and exceeds the number + of bits alloted to contain the result. This is typically + caused by low--order truncation} +} + + + + + +\newacronym{msb}{MSB}{Most Significant Bit} +\newacronym{lsb}{LSB}{Least Significant Bit} +\newacronym{isa}{ISA}{Instruction Set Architecture} diff --git a/book/insnformats.tex b/book/insnformats.tex new file mode 100644 index 0000000..f77d3d2 --- /dev/null +++ b/book/insnformats.tex @@ -0,0 +1,442 @@ + +\def\SignBoxCornerRadius{.75mm} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\newcommand\BeginTikzPicture{ + \begin{tikzpicture}[x=.4cm,y=.3cm] +} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\newcommand\EndTikzPicture{ + \end{tikzpicture} +} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% Print the characters within a string evenly spaced at integral node positions +% +% #1 The number of characters in the string +\newcommand\DrawBitstring[2]{ +\foreach \x in {1,...,#1}% + \draw(\x,0) node{\substring{#2}{\x}{\x}};% +} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% #1 The total size +% #2 The string to print +% #3 The value to use when extending to left +\newcommand\DrawLeftExtendedBitstring[3]{ + \StrLen{#2}[\numchars] + + \pgfmathsetmacro\leftpadd{int(#1-\numchars)} + \foreach \x in {1,...,\leftpadd} + \draw(\x,0) node{#3}; + + \pgfmathsetmacro\leftpadd{int(\leftpadd+1)} + \foreach \x in {\leftpadd,...,#1} + \pgfmathsetmacro\ix{int(\x-\leftpadd+1)} + \draw(\x,0) node{\substring{#2}{\ix}{\ix}}; +} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% If the string is shorter than expected, extend with #5 to the right. +% +% #1 The total size +% #2 Num chars to extend on the right +% #3 The string to print +% #4 The value to use when extending to left +% #5 The value to use when extending to right +\newcommand\DrawDoubleExtendedBitstring[5]{ + \StrLen{#3}[\numchars] + + \pgfmathsetmacro\leftpadd{int(#1-#2-\numchars)} + \ifthenelse{1 > \leftpadd} + {} + { + \foreach \x in {1,...,\leftpadd} + \draw(\x,0) node{#4}; + } + + \pgfmathsetmacro\leftpadd{int(\leftpadd+1)} + \pgfmathsetmacro\rightpadd{int(\leftpadd+\numchars)} + \foreach \x in {\leftpadd,...,\rightpadd} + \pgfmathsetmacro\ix{int(\x-\leftpadd+1)} + \draw(\x,0) node{\substring{#3}{\ix}{\ix}}; + + + %\pgfmathsetmacro\rightpadd{int(\rightpadd+1)} + \ifthenelse{\rightpadd > #1} + {} + { + \foreach \x in {\rightpadd,...,#1} + \draw(\x,0) node{#5}; + } +} + + + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% Draw a box suitable to show the given number of bits in a +% labeled box suitable for showing expanded binary numbers. +% +% #1 The number of characters to display +\newcommand\DrawBitBox[1]{ + \draw (.5,-.75) -- (#1+.5,-.75); % box bottom + \draw (.5,.75) -- (#1+.5,.75); % box top + \draw (.5,-.75) -- (.5, 1.5); % left end + \draw (#1+.5,-.75) -- (#1+.5, 1.5); % right end + \pgfmathsetmacro\result{int(#1-1)} % calc high bit + \node at (1,1.2) {\tiny\result}; % high bit label + \draw(#1,1.2) node{\tiny0}; % low bit label + + \pgfmathsetmacro\result{#1/2} + \node at (\result,-1.2) {\tiny#1}; % size below the box + + \pgfmathsetmacro\result{#1/2} + \draw[->] (\result+.6,-1.2) -- (#1+.5,-1.2); + \draw[->] (\result-.6,-1.2) -- (.5,-1.2); +} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\newcommand\DrawBitBoxUnsigned[1]{ + \StrLen{#1}[\numchars] + \DrawBitBox{\numchars} + \DrawBitstring{\numchars}{#1} % show the bits +} + + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\newcommand\DrawBitBoxUnsignedPicture[1]{ + \BeginTikzPicture + \DrawBitBoxUnsigned{#1} + \EndTikzPicture +} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\newcommand\DrawBitBoxSignedPicture[1]{ + \BeginTikzPicture + \DrawBitBoxUnsigned{#1} + % draw a box around the sign bit + \draw {[rounded corners=\SignBoxCornerRadius] (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle}; + \EndTikzPicture +} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% #1 The total (extended) size +% #2 The value to use for left-side padding +% #3 The string to extend +\newcommand\DrawBitBoxLeftExtended[3]{ + \StrLen{#3}[\numchars] + \pgfmathsetmacro\fill{int(#1-\numchars)} + \begin{scope}[shift={(\fill,3.5)}] + \DrawBitBoxUnsigned{#3} + + % XXX IFF not zero-extending then draw a box around the sign bit + \draw {[rounded corners=\SignBoxCornerRadius] (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle}; + \end{scope} + + \DrawBitBox{#1} + \DrawDoubleExtendedBitstring{#1}{0}{#3}{#2}{x} + + % XXX IFF not zero-extending then draw a box around the sign bit + \draw {[rounded corners=\SignBoxCornerRadius] (\fill+1.35, -.6) -- (\fill+1.35, .6) -- (\fill+.65, .6) -- (\fill+.65, -.6) -- cycle}; + % draw a box around the extended sign bits + \draw (.65, -.6) -- (.65, .6) -- (\fill+.35, .6) -- (\fill+.35, -.6) -- cycle; + + +} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\newcommand\DrawBitBoxSignExtendedPicture[2]{ + \BeginTikzPicture + \DrawBitBoxLeftExtended{#1}{\substring{#2}{1}{1}}{#2} + \EndTikzPicture +} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\newcommand\DrawBitBoxZeroExtendedPicture[2]{ + \BeginTikzPicture + \DrawBitBoxLeftExtended{#1}{0}{#2} + \EndTikzPicture +} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% #1 Total bit length +% #2 The string to print +% #3 Right-side padding length +\newcommand\DrawBitBoxSignLeftZeroRightExtendedPicture[3]{ + \BeginTikzPicture + + \StrLen{#2}[\numchars] + \pgfmathsetmacro\fill{int(#1-\numchars-#3)} + \begin{scope}[shift={(\fill,3.5)}] + \DrawBitBoxUnsigned{#2} + % draw a box around the sign bit + %\draw (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle; + \draw {[rounded corners=\SignBoxCornerRadius] (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle}; + \end{scope} + + \DrawBitBox{#1} + \DrawDoubleExtendedBitstring{#1}{#3}{#2}{\substring{#2}{1}{1}}{0} + + % Box the sign bit + \draw {[rounded corners=\SignBoxCornerRadius] (\fill+1.35, -.6) -- (\fill+1.35, .6) -- (\fill+.65, .6) -- (\fill+.65, -.6) -- cycle}; + + \ifthenelse{\fill > 0} + { + % Box the left-extended sign bits + \draw (.65, -.6) -- (.65, .6) -- (\fill+.35, .6) -- (\fill+.35, -.6) -- cycle; + % \fill[blue!40!white] (.65, -.6) rectangle (\fill-.25, 1.2); + } + {} + \ifthenelse{#3 > 0} + { + % Box the right-extended sign bits + \pgfmathsetmacro\posn{int(\numchars+\fill)} + \draw (\posn+.65, -.6) -- (\posn+.65, .6) -- (\posn+#3+.35, .6) -- (\posn+#3+.35, -.6) -- cycle; + } + {} + + + \EndTikzPicture +} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% Print the characters within a string evenly spaced at integral node positions +% +% #1 The number of characters in the string +% #2 The string of characters to plot +\newcommand\DrawInsnBitstring[3]{ + \pgfmathsetmacro\num{int(#1-1)} + \foreach \x in {1,2,...,#1} + \draw(\x,0) node{\substring{#2}{\x}{\x}}; + + \draw(#1+1,0) node[right]{#3}; +} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% Draw a bit-separator line with labels at the given bit-offset (from the right) +% +% #1 Total box width +% #2 The position that the sepatator will be drawn to the left. +\newcommand\DrawInsnBoxSep[2]{ + \draw (#1-#2-.5,-.75) -- (#1-#2-.5, 1.5); + \node at (#1-#2,1.2) {\tiny#2}; + \pgfmathsetmacro\result{int(#2+1)} + \node at (#1-#2-1,1.2) {\tiny\result}; +} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% #1 total characters/width +% #2 MSB position +% #3 LSB position +% #4 the segment label +\newcommand\DrawInsnBoxSeg[4]{ + \pgfmathsetmacro\leftpos{int(#1-#2)} + \pgfmathsetmacro\rightpos{int(#1-#3)} + + \draw (\leftpos-.5,-.75) -- (\rightpos+.5,-.75); % box bottom + \draw (\leftpos-.5,1.75) -- (\rightpos+.5,1.75); % box top + \draw (\leftpos-.5,-.75) -- (\leftpos-.5, 2.5); % left end + \draw (\rightpos+.5,-.75) -- (\rightpos+.5, 2.5); % right end + \node at (\leftpos,2.2) {\tiny#2}; + \draw(\rightpos,2.2) node{\tiny#3}; + + \pgfmathsetmacro\posn{#1-#2+(#2-#3)/2} + \pgfmathsetmacro\range{int(#2-#3+1)} + \node at (\posn,-1.4) {\small\range}; % the field width + \node at (\posn,1.2) {\small#4}; % the field label + +% % arrows showing the span of the bits... meh +% \draw[->] (\posn+.5,-1.4) -- (\rightpos+.2,-1.4); +% \draw[->] (\posn-.5,-1.4) -- (\leftpos-.2,-1.4); +} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\newcommand\InsnStatement[1]{ +% \textbf{\large #1}\\ +% \textbf{#1}\\ + {\large #1}\\ +} +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% #1 the binary encoding +\newcommand\DrawInsnTypeBTikz[1]{ + \BeginTikzPicture + \StrLen{#1}[\numchars] + \DrawInsnBitstring{\numchars}{#1}{\hyperref[insnformat:btype]{B-type}} + \DrawInsnBoxSeg{\numchars}{31}{25}{imm[12\textbar10:5]} + \DrawInsnBoxSeg{\numchars}{24}{20}{rs2} + \DrawInsnBoxSeg{\numchars}{19}{15}{rs1} + \DrawInsnBoxSeg{\numchars}{14}{12}{funct3} + \DrawInsnBoxSeg{\numchars}{11}{7}{imm[4:1\textbar11]} + \DrawInsnBoxSeg{\numchars}{6}{0}{opcode} + + % add some hint bits in for imm fields + \draw {[rounded corners=\SignBoxCornerRadius] (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle}; % sign bit + \draw (32-7-.5, -.75) -- (32-7-.5, .1); % imm[11] + + \EndTikzPicture +} + +\newcommand\DrawInsnTypeBPicture[2]{ + \InsnStatement{#1}\\ + \DrawInsnTypeBTikz{#2} +} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% #1 the binary encoding +\newcommand\DrawInsnTypeUTikz[1]{ + \BeginTikzPicture + \StrLen{#1}[\numchars] + \DrawInsnBitstring{\numchars}{#1}{\hyperref[insnformat:utype]{U-type}} + \DrawInsnBoxSeg{\numchars}{31}{12}{imm[31:12]} + \DrawInsnBoxSeg{\numchars}{11}{7}{rd} + \DrawInsnBoxSeg{\numchars}{6}{0}{opcode} + + % add some hint bits in for imm fields + \draw {[rounded corners=\SignBoxCornerRadius] (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle}; % sign bit + + \EndTikzPicture +} + +\newcommand\DrawInsnTypeUPicture[2]{ + \InsnStatement{#1}\\ + \DrawInsnTypeUTikz{#2} +} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% #1 the binary encoding +\newcommand\DrawInsnTypeJTikz[1]{ + \BeginTikzPicture + \StrLen{#1}[\numchars] + \DrawInsnBitstring{\numchars}{#1}{\hyperref[insnformat:jtype]{J-type}} + \DrawInsnBoxSeg{\numchars}{31}{12}{imm[20\textbar10:1\textbar11\textbar19:12]} + \DrawInsnBoxSeg{\numchars}{11}{7}{rd} + \DrawInsnBoxSeg{\numchars}{6}{0}{opcode} + + % add some hint bits in for imm fields + \draw {[rounded corners=\SignBoxCornerRadius] (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle}; % sign bit + \draw (32-19-.5, -.75) -- (32-19.5, .1); % imm[19:12] + \draw (32-20-.5, -.75) -- (32-20.5, .1); % imm[11] + + \EndTikzPicture +} + +\newcommand\DrawInsnTypeJPicture[2]{ + \InsnStatement{#1}\\ + \DrawInsnTypeJTikz{#2} +} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% #1 the binary encoding +\newcommand\DrawInsnTypeI[1]{ + \StrLen{#1}[\numchars] + \DrawInsnBitstring{\numchars}{#1}{\hyperref[insnformat:itype]{I-type}} + \DrawInsnBoxSeg{\numchars}{31}{20}{imm[11:0]} + \DrawInsnBoxSeg{\numchars}{19}{15}{rs1} + \DrawInsnBoxSeg{\numchars}{14}{12}{funct3} + \DrawInsnBoxSeg{\numchars}{11}{7}{rd} + \DrawInsnBoxSeg{\numchars}{6}{0}{opcode} + + % add some hint bits in for imm fields + \draw {[rounded corners=\SignBoxCornerRadius] (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle}; % sign bit +} +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% #1 the binary encoding +\newcommand\DrawInsnTypeITikz[1]{ + \BeginTikzPicture + \DrawInsnTypeI{#1} + \EndTikzPicture +} +\newcommand\DrawInsnTypeIPicture[2]{ + \InsnStatement{#1}\\ + \DrawInsnTypeITikz{#2} +} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% #1 the binary encoding +\newcommand\DrawInsnTypeSTikz[1]{ + \BeginTikzPicture + \StrLen{#1}[\numchars] + \DrawInsnBitstring{\numchars}{#1}{\hyperref[insnformat:stype]{S-type}} + \DrawInsnBoxSeg{\numchars}{31}{25}{imm[11:5]} + \DrawInsnBoxSeg{\numchars}{24}{20}{rs2} + \DrawInsnBoxSeg{\numchars}{19}{15}{rs1} + \DrawInsnBoxSeg{\numchars}{14}{12}{funct3} + \DrawInsnBoxSeg{\numchars}{11}{7}{imm[4:0]} + \DrawInsnBoxSeg{\numchars}{6}{0}{opcode} + + % add some hint bits in for imm fields + \draw {[rounded corners=\SignBoxCornerRadius] (1.35, -.6) -- (1.35, .6) -- (.65, .6) -- (.65, -.6) -- cycle}; % sign bit + + \EndTikzPicture +} + +\newcommand\DrawInsnTypeSPicture[2]{ + \InsnStatement{#1}\\ + \DrawInsnTypeSTikz{#2} +} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% #1 the binary encoding +\newcommand\DrawInsnTypeRShiftTikz[1]{ + \BeginTikzPicture + \StrLen{#1}[\numchars] + \DrawInsnBitstring{\numchars}{#1}{\hyperref[insnformat:rtype]{R-type}} + \DrawInsnBoxSeg{\numchars}{31}{25}{funct7} + \DrawInsnBoxSeg{\numchars}{24}{20}{shamt} + \DrawInsnBoxSeg{\numchars}{19}{15}{rs1} + \DrawInsnBoxSeg{\numchars}{14}{12}{funct3} + \DrawInsnBoxSeg{\numchars}{11}{7}{rd} + \DrawInsnBoxSeg{\numchars}{6}{0}{opcode} + + \EndTikzPicture +} + +\newcommand\DrawInsnTypeRShiftPicture[2]{ + \InsnStatement{#1}\\ + \DrawInsnTypeRShiftTikz{#2} +} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% #1 the binary encoding +\newcommand\DrawInsnTypeRTikz[1]{ + \BeginTikzPicture + \StrLen{#1}[\numchars] + \DrawInsnBitstring{\numchars}{#1}{\hyperref[insnformat:rtype]{R-type}} + \DrawInsnBoxSeg{\numchars}{31}{25}{funct7} + \DrawInsnBoxSeg{\numchars}{24}{20}{rs2} + \DrawInsnBoxSeg{\numchars}{19}{15}{rs1} + \DrawInsnBoxSeg{\numchars}{14}{12}{funct3} + \DrawInsnBoxSeg{\numchars}{11}{7}{rd} + \DrawInsnBoxSeg{\numchars}{6}{0}{opcode} + + \EndTikzPicture +} + +\newcommand\DrawInsnTypeRPicture[2]{ + \InsnStatement{#1}\\ + \DrawInsnTypeRTikz{#2} +} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + + +% print a register name in typewriter font +\newcommand\reg[1]{{\tt #1}} + + diff --git a/book/intro/chapter.tex b/book/intro/chapter.tex new file mode 100644 index 0000000..49e8e3d --- /dev/null +++ b/book/intro/chapter.tex @@ -0,0 +1,10 @@ +\chapter{Introduction} +\label{chapter:Introduction} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\section{Instruction Set Architecture} + +Discuss the IMAFD, G and other ISA extensions mean. + + diff --git a/book/license/chapter.tex b/book/license/chapter.tex new file mode 100644 index 0000000..7d4e7e7 --- /dev/null +++ b/book/license/chapter.tex @@ -0,0 +1,427 @@ +\chapter{Attribution 4.0 International} +\label{license} + +\begin{scriptsize} + +Creative Commons Corporation ("Creative Commons") is not a law firm and +does not provide legal services or legal advice. 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Term and Termination} + +\begin{itemize} +\item[a.] This Public License applies for the term of the Copyright and + Similar Rights licensed here. However, if You fail to comply with + this Public License, then Your rights under this Public License + terminate automatically. + +\item[b.] Where Your right to use the Licensed Material has terminated under + Section 6(a), it reinstates: + + \begin{itemize} + \item[1.] automatically as of the date the violation is cured, provided + it is cured within 30 days of Your discovery of the + violation; or + + \item[2.] upon express reinstatement by the Licensor. + \end{itemize} + + For the avoidance of doubt, this Section 6(b) does not affect any + right the Licensor may have to seek remedies for Your violations + of this Public License. + +\item[c.] For the avoidance of doubt, the Licensor may also offer the + Licensed Material under separate terms or conditions or stop + distributing the Licensed Material at any time; however, doing so + will not terminate this Public License. + +\item[d.] Sections 1, 5, 6, 7, and 8 survive termination of this Public + License. +\end{itemize} + + +\subsection*{Section 7. Other Terms and Conditions} + +\begin{itemize} +\item[a.] The Licensor shall not be bound by any additional or different + terms or conditions communicated by You unless expressly agreed. + +\item[b.] Any arrangements, understandings, or agreements regarding the + Licensed Material not stated herein are separate from and + independent of the terms and conditions of this Public License. +\end{itemize} + +\subsection*{Section 8. Interpretation} + +\begin{itemize} +\item[a.] For the avoidance of doubt, this Public License does not, and + shall not be interpreted to, reduce, limit, restrict, or impose + conditions on any use of the Licensed Material that could lawfully + be made without permission under this Public License. + +\item[b.] To the extent possible, if any provision of this Public License is + deemed unenforceable, it shall be automatically reformed to the + minimum extent necessary to make it enforceable. If the provision + cannot be reformed, it shall be severed from this Public License + without affecting the enforceability of the remaining terms and + conditions. + +\item[c.] No term or condition of this Public License will be waived and no + failure to comply consented to unless expressly agreed to by the + Licensor. + +\item[d.] Nothing in this Public License constitutes or may be interpreted + as a limitation upon, or waiver of, any privileges and immunities + that apply to the Licensor or You, including from the legal + processes of any jurisdiction or authority.\\ +\end{itemize} + +\hrule + +Creative Commons is not a party to its public +licenses. Notwithstanding, Creative Commons may elect to apply one of +its public licenses to material it publishes and in those instances +will be considered the Licensor. The text of the Creative Commons +public licenses is dedicated to the public domain under the CC0 Public +Domain Dedication. Except for the limited purpose of indicating that +material is shared under a Creative Commons public license or as +otherwise permitted by the Creative Commons policies published at +\url{http://creativecommons.org/policies}, Creative Commons does not authorize the +use of the trademark ``Creative Commons'' or any other trademark or logo +of Creative Commons without its prior written consent including, +without limitation, in connection with any unauthorized modifications +to any of its public licenses or any other arrangements, +understandings, or agreements concerning use of licensed material. For +the avoidance of doubt, this paragraph does not form part of the +public licenses. + +Creative Commons may be contacted at \url{http://creativecommons.org}. + +\end{scriptsize} diff --git a/book/numbers/chapter.tex b/book/numbers/chapter.tex new file mode 100644 index 0000000..98918f9 --- /dev/null +++ b/book/numbers/chapter.tex @@ -0,0 +1,750 @@ +\chapter{Number Systems} +\label{chapter:NumberSystems} + +RISC-V systems represent information using binary values stored in +little-endian order.\footnote{See\cite{IEN137} for some history of +the big/little-endian ``controversy.''} + +\section{Integers} + +A binary integer is constructed with only 1s and 0s in the same +manner as decimal numbers are constructed with values from 0 to 9. + +Counting in binary is the same as in decimal. For example, when +adding 1 to 9, the carry is added to the next place value. When +subtracting 1 from 0, a borrow is required and so on. + +Figure~\autoref{Figure:integers} shows an abridged table of the +decimal, binary and hexadecimal values from 0 to 129. + +\begin{figure}[ht] +\begin{center} +\begin{tabular}{|c|c|c||c|c|c|c|c|c|c|c||c|c|} +\hline +\multicolumn{3}{|c||}{Decimal} & \multicolumn{8}{|c||}{Binary} & \multicolumn{2}{|c|}{Hex}\\ +\hline +$10^2$ & $10^1$ & $10^0$ & $2^7$ & $2^6$ & $2^5$ & $2^4$ & $2^3$ & $2^2$ & $2^1$ & $2^0$ & $16^1$ & $16^0$ \\ +\hline +100 & 10 & 1 & 128 & 64 & 32 & 16 & 8 & 4 & 2 & 1 & 16 & 1 \\ +\hline \hline +0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ +0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 1 \\ +0 & 0 & 2 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 2 \\ +0 & 0 & 3 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 0 & 3 \\ +0 & 0 & 4 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 4 \\ +0 & 0 & 5 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 1 & 0 & 5 \\ +0 & 0 & 6 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 0 & 0 & 6 \\ +0 & 0 & 7 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 0 & 7 \\ +0 & 0 & 8 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 8 \\ +0 & 0 & 9 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 0 & 9 \\ +0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 1 & 0 & 0 & a \\ +0 & 1 & 1 & 0 & 0 & 0 & 0 & 1 & 0 & 1 & 1 & 0 & b \\ +0 & 1 & 2 & 0 & 0 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & c \\ +0 & 1 & 3 & 0 & 0 & 0 & 0 & 1 & 1 & 0 & 1 & 0 & d \\ +0 & 1 & 4 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 0 & 0 & e \\ +0 & 1 & 5 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & f \\ +0 & 1 & 6 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 1 & 0 \\ +0 & 1 & 7 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 1 & 1 & 1 \\ +\hline +\multicolumn{3}{|c||}{\ldots} & \multicolumn{8}{|c||}{\ldots} & \multicolumn{2}{|c|}{\ldots}\\ +\hline +1 & 2 & 5 & 0 & 1 & 1 & 1 & 1 & 1 & 0 & 1 & 7 & d \\ +1 & 2 & 6 & 0 & 1 & 1 & 1 & 1 & 1 & 1 & 0 & 7 & e \\ +1 & 2 & 7 & 0 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 7 & f \\ +1 & 2 & 8 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 8 & 0 \\ +\hline +\end{tabular} +\end{center} +\captionof{figure}{Counting in decimal, binary and hexadecimal.} +\label{Figure:integers} +\end{figure} + + +One way to look at this table is on a per--row basis where each place +value is represented by the base raised to the power of the place value +position (shown in the column headings.) This is useful when +converting arbitrary values between bases. For example to interpret +the decimal value on the fourth row: +\[ 0 \times 10^2 + 0 \times 10^1 + 3 \times 10^0 = 3_{10} \] +And to interpret binary value on the same row by converting it to decimal: +\[ 0 \times 2^7 + 0 \times 2^6 +0 \times 2^5 +0 \times 2^4 +0 \times 2^3 +0 \times 2^2 + 1 \times 2^1 + 1 \times 2^0 = 3_{10} \] +And the same for the hexadecimal value: +\[ 0 \times 16^1 + 3 \times 16^0 = 3_{10} \] + + +Another way to look at this table is on a per--column basis. When +tasked with drawing such a table by hand, it might be useful +to observe that, just as in decimal, the right--most column will +cycle through all of the values represented in the chosen base +then cycle back to zero and repeat. (For example, in binary this +pattern is 0-1-0-1-0-1-0-\ldots) The next column in each base +will cycle in the same manner except each of the values is repeated +as many times as is represented by the place value (in the case of +decimal, $10^1$ times, binary $2^1$ times, hex $16^1$ times. Again, +the for binary numbers this pattern is 0-0-1-1-0-0-1-1-\ldots) +This continues for as many columns as are needed to represent the +magnitude of the desired number. + +Another item worth noting is that any even binary number will always +have a 0 LSB and odd numbers will always have a 1 LSB. + +As is customary in decimal, leading zeroes are sometimes not shown +for readability. + +The relationship between binary and hex values is also worth taking +note. Because $2^4 = 16$, there is a clean and simple grouping +of 4 \gls{bit}s to 1 \gls{hit}. There is no such relationship +between binary and decimal. + +Writing and reading numbers in binary that are longer than 8 bits +is cumbersome and prone to error. The simple conversion between +binary and hex makes hex a convenient shorthand for expressing +binary values in many situations. + +For example, consider the following value expressed in binary, +hexadecimal and decimal (spaced to show the relationship +between binary and hex): + +\begin{verbatim} +Binary value: 0010 0111 1011 1010 1100 1100 1111 0101 +Hex Value: 2 7 B A C C F 5 +Decimal Value: 666553589 +\end{verbatim} + +Empirically we can see that grouping the bits into sets of four +allows an easy conversion to hex and expressing it as such is +$\frac{1}{4}$ as long as in binary while at the same time +allowing for easy conversion back to binary. + +The decimal value in this example does not easily convey a sense +of the binary value. + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Converting Between Bases} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsubsection{From Binary to Decimal} +\label{section:bindec} + +Alas, it is occasionally necessary to convert between decimal, +binary and/or hex. + +To convert from binary to decimal, put the decimal value of the place values +{\ldots8 4 2 1} over the binary digits like this: + +\begin{verbatim} + 128 64 32 16 8 4 2 1 + 0 0 0 1 1 0 1 1 +\end{verbatim} + +Now sum the place--values that are expressed in decimal for each +bit with the value of 1: $16+8+2+1$. The integer binary value +$00011011_2$ represents the decimal value $27_{10}$. + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsubsection{From Binary to Hexadecimal} +\label{section:binhex} + +Conversion from binary to hex involves grouping the bits into +sets of four and then performing the same summing process as +shown above. If there is not a multiple of four bits then +extend the binary to the left with zeroes to make it so. + +Grouping the bits into sets of four and summing: + +\begin{verbatim} +Place: 8 4 2 1 8 4 2 1 8 4 2 1 8 4 2 1 +Binary: 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 0 +Decimal: 4+2 =6 8+4+ 1=13 8+ 2 =10 8+4+2 =14 +\end{verbatim} + +After the summing, convert each decimal value to hex. The decimal +values from 0--9 are the same values in hex. Because we don't have any +more numerals to represent the values from 10-15, we use the first 6 +letters (See the right--most column of \autoref{Figure:integers}.) +Fortunately there are only six hex mappings involving letters. Thus +it is reasonable to memorize them. + +Continuing this example: + +\begin{verbatim} +Decimal: 6 13 10 14 +Hex: 6 D A E +\end{verbatim} + + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsubsection{From Hexadecimal to Binary} + +Again, the four--bit mapping between binary and hex makes this +task as straight forward as using a look-up table. + +For each \gls{hit} (Hex digIT), translate it to its unique four--bit pattern. +Perform this task either by memorizing each of the 16 patterns +or by converting each hit to decimal first and then converting +each four--bit binary value to decimal using the place--value summing +method discussed in \autoref{section:bindec}. + +For example: + +\begin{verbatim} +Hex: 4 C +Binary: 0 1 0 0 1 1 0 0 +Decimal: 128 64 32 16 8 4 2 1 +Sum: 64+ 8+4 = 76 +\end{verbatim} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsubsection{From Decimal to Binary} + +To convert arbitrary decimal numbers to binary, extend the list +of binary place values until it exceeds the value of the decimal +number being converted. Then make successive subtractions of each +of the place values that would yield a non-negative result. + +For example, to convert $1234_{10}$ to binary: + +\begin{verbatim} +Place values: 2048-1024-512-256-128-64-32-16-8-4-2-1 + + 0 2048 (too big) + 1 1234 - 1024 = 210 + 0 512 (too big) + 0 256 (too big) + 1 210 - 128 = 82 + 1 82 - 64 = 18 + 0 32 (too big) + 1 18 - 16 = 2 + 0 8 (too big) + 0 4 (too big) + 1 2 - 2 = 0 + 0 1 (too big) +\end{verbatim} + +The answer using this notation is listed vertically +in the left column with the \acrshort{msb} on the top and +the \acrshort{lsb} on the bottom line: $010011010010_2$. + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsubsection{From Decimal to Hex} + +Conversion from decimal to hex can be done by using the place +values for base--16 and the same math as from decimal to binary +or by first converting the decimal value to binary and then +from binary to hex by using the methods discussed above. + +Because binary and hex are so closely related, performing +a conversion by way of binary is quite straight forward. + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Addition of Binary Numbers} + +The addition of binary numbers can be performed long--hand the +same way decimal addition is taught in grade school. In fact binary +addition is easier since it only involves adding 0 or 1. + +The first thing to note that in any number base $0+0=0$, $0+1=1$, and +$1+0=1$. Since there is no ``two'' in binary (just like there is +no ``ten'' decimal) adding $1+1$ results in a zero with a carry as +in: $1+1=10_2$ and in: $1+1+1=11_2$. Using these five sums, any two +binary integers can be added. + +For example: + +\begin{verbatim} + 111111 1111 <== carries + 0110101111001111 <== addend + + 0000011101100011 <== addend + ------------------ + 0111001100110010 <== sum +\end{verbatim} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Signed Numbers} + +There are multiple methods used to represent signed binary integers. +The method used by most modern computers is called ``two's complement.'' + +A two's complement number is encoded in such a manner as to simplify +the hardware used to add, subtract and compare integers. + +A simple method of thinking about two's complement numbers is to +negate the place value of the \acrshort{msb}. For example, the +number one is represented the same as discussed before: + +\begin{verbatim} + -128 64 32 16 8 4 2 1 + 0 0 0 0 0 0 0 1 +\end{verbatim} + +The \acrshort{msb} of any negative number in this format will always +be 1. For example the value $-1_{10}$ is: + +\begin{verbatim} + -128 64 32 16 8 4 2 1 + 1 1 1 1 1 1 1 1 +\end{verbatim} + +\ldots because: $-128+64+32+16+8+4+2+1=-1$. + +This format has the virtue of allowing the same addition logic +discussed above to be used to calculate $-1+1=0$. + +\begin{verbatim} + -128 64 32 16 8 4 2 1 <== place value + 1 1 1 1 1 1 1 1 0 <== carries + 1 1 1 1 1 1 1 1 <== addend (-1) + + 0 0 0 0 0 0 0 1 <== addend (1) + ---------------------- + 1 0 0 0 0 0 0 0 0 <== sum (0 with an overflow) +\end{verbatim} + +In order for this to work, the \gls{overflow} carry out of the +sum of the MSBs is ignored. + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsubsection{Converting between Positive and Negative} + +Changing the sign on two's complement numbers can be described as +inverting all of the bits (which is also known as the one's complement) +and then add one. + +For example, inverting the number {\em four}: + +\begin{verbatim} + -128 64 32 16 8 4 2 1 + 0 0 0 0 0 1 0 0 <== 4 + + 1 1 <== carries + 1 1 1 1 1 0 1 1 <== one's complement of 4 + + 0 0 0 0 0 0 0 1 <== plus 1 + ---------------------- + 1 1 1 1 1 1 0 0 <== -4 +\end{verbatim} + +This can be verified by adding 5 to the result and observe that +the sum is 1: + +\begin{verbatim} + -128 64 32 16 8 4 2 1 + 1 1 1 1 1 <== carries + 1 1 1 1 1 1 0 0 <== -4 + + 0 0 0 0 0 1 0 1 <== 5 + ---------------------- + 1 0 0 0 0 0 0 0 1 +\end{verbatim} + +Note that the changing of the sign using this method is symmetric +in that it is identical when converting from negative to positive +and when converting from positive to negative: flip the bits and +add 1. + +For example, changing the value -4 to 4 to illustrate the +reverse of the conversion above: + +\begin{verbatim} + -128 64 32 16 8 4 2 1 + 1 1 1 1 1 1 0 0 <== -4 + + 1 1 <== carries + 0 0 0 0 0 0 1 1 <== one's complement of -4 + + 0 0 0 0 0 0 0 1 <== plus 1 + ---------------------- + 0 0 0 0 0 1 0 0 <== 4 +\end{verbatim} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Subtraction of Binary Numbers} + + +Subtraction of binary numbers is performed by first negating +the subtrahend and then adding the two numbers. Due to the +nature of two's complement numbers this will work for both +signed and unsigned numbers. +\enote{This section needs more examples of subtracting +signed an unsigned numbers and a discussion on how +signedness is not relevant until the results are interpreted. +For example adding $-4+ -8=-12$ using two 8--bit numbers +is the same as adding $252+248=500$ and truncating the result +to 244.} + +To calculate $-4-8 = -12$ + +\begin{verbatim} + -128 64 32 16 8 4 2 1 + 1 1 1 1 1 1 0 0 <== -4 + - 0 0 0 0 1 0 0 0 <== 8 + + + 1 1 1 <== carries + 1 1 1 1 0 1 1 1 <== one's complement of -8 + + 0 0 0 0 0 0 0 1 <== plus 1 + ---------------------- + 1 1 1 1 1 0 0 0 <== -8 + + + 1 1 1 1 <== carries + 1 1 1 1 1 1 0 0 <== -4 + + 1 1 1 1 1 0 0 0 <== -8 + ---------------------- + 1 1 1 1 1 0 1 0 0 < == -12 +\end{verbatim} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Truncation and Overflow} + +Disscuss the details of truncation and overflow here. +\enote{This chapter should be made consistent in its use of +{\em truncation} and {\em overflow} as occur with signed and unsigned +addition and subtraction.} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Logical/Boolean Functions} + +Unlike addition and subtraction, boolean functions apply +on a per--bit basis. +%in that they do not impact neighboring bits. +%by generating things like a carry or a borrow. +When applied to multi--bit values, each bit position is operated upon +independantly of the other bits. +\enote{This is unclear. Need to define bit positions and probably +should add basic truth table diagrams.} +\enote{Need to define 1 as true and 0 as false somewhere.} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsubsection{NOT} + +The {\em NOT} operator applies to a single operand and represents the +opposite of the input. +\enote{Need to define unary, binary and ternary operators without +confusing binary operators with binary numbers.} + +If the input is 1 then the output is 0. If the input is 0 then the +output is 1. In other words, the output value is {\em not} that of the +input value. + +This text will use the operator used in the C language when discussing +the {\em NOT} operator in symbolic form. Specifically the tilde: `\verb@~@'. + +\begin{verbatim} + ~ 1 1 1 1 0 1 0 1 <== A + ----------------- + 0 0 0 0 1 0 1 0 <== output +\end{verbatim} + +In a line of code the above might read like this: \verb@output = ~A@ + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsubsection{AND} + +The boolean {\em and} function has two or more inputs and the output is a +single bit. The output is 1 if and only if all of the input values are 1. +Otherwise it is 0. + +This text will use the operator used in the C language when discussing +the {\em AND} operator in symbolic form. Specifically the ampersand: `\verb@&@'. + +This function works like it does in spoken language. For example +if A is 1 {\em AND} B is 1 then the output is 1 (true). +Otherwise the output is 0 (false). For example: + +\begin{verbatim} + 1 1 1 1 0 1 0 1 <== A + & 1 0 0 1 0 0 1 1 <== B + ----------------- + 1 0 0 1 0 0 0 1 <== output +\end{verbatim} + +In a line of code the above might read like this: \verb@output = A & B@ + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsubsection{OR} + +The boolean {\em or} function has two or more inputs and the output is a +single bit. The output is 1 if at least one of the input values are 1. + +This text will use the operator used in the C language when discussing +the {\em OR} operator in symbolic form. Specifically the pipe: `\verb@|@'. + +This function works like it does in spoken language. For example +if A is 1 {\em OR} B is 1 then the output is 1 (true). +Otherwise the output is 0 (false). For example: + +\begin{verbatim} + 1 1 1 1 0 1 0 1 <== A + | 1 0 0 1 0 0 1 1 <== B + ----------------- + 1 1 1 1 0 1 1 1 <== output +\end{verbatim} + +In a line of code the above might read like this: \verb@output = A | B@ + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsubsection{XOR} + +The boolean {\em exclusive or} function has two or more inputs and the +output is a single bit. The output is 1 if only an odd number of inputs +are 1. Otherwise the output will be 0. + +This text will use the operator used in the C language when discussing +the {\em XOR} operator in symbolic form. Specifically the carrot: `\verb@^@'. + +Note that when {\em XOR} is used with two inputs, the output +is set to 1 (true) when the inputs have different values and 0 +(false) when the inputs both have the same value. + +For example: + +\begin{verbatim} + 1 1 1 1 0 1 0 1 <== A + ^ 1 0 0 1 0 0 1 1 <== B + ----------------- + 0 1 1 0 0 1 1 0 <== output +\end{verbatim} + +In a line of code the above might read like this: \verb@output = A ^ B@ + + + +%\section{Context} +% +%Numbers can be interpreted differently depending on the context in +%which they are used. For example a number may represent the quantity +%of millimeters between two points. It may enumerate a +%a letter of the alphabet -- ie. $01000001=A$, $01000010=B$, +%$01000011=C$\ldots\ In fact, any finite set of items can be identified +%(enumerated) by a assigning a code number to each element in this fashon. + + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\section{IEEE-754 Floating Point Number Representation} +\label{chapter::floatingpoint} + +This section provides an overview of the IEEE-754 32-bit binary floating +point format. + +\begin{itemize} +\item Recall that the place values for integer binary numbers are: +\begin{verbatim} + ... 128 64 32 16 8 4 2 1 +\end{verbatim} +\item We can extend this to the right in binary similar to the way we do for +decimal numbers: +\begin{verbatim} + ... 128 64 32 16 8 4 2 1 . 1/2 1/4 1/8 1/16 1/32 1/64 1/128 ... +\end{verbatim} +The `.' in a binary number is a binary point, not a decimal point. + +\item We use scientific notation as in $2.7 \times 10^{-47}$ to express either +small fractions or large numbers when we are not concerned every last digit +needed to represent the entire, exact, value of a number. + +\item The format of a number in scientific notation is $mantissa \times base^{exponent}$ + +\item In binary we have $mantissa \times 2^{exponent}$ + +\item IEEE--754 format requires binary numbers to be {\em normalized} to +$1.significand \times 2^{exponent}$ where the {\em significand} +is the portion of the {\em mantissa} that is to the right of the binary--point. + +\begin{itemize} +\item The unnormalized binary value of $-2.625$ is $10.101$ +\item The normalized value of $-2.625$ is $1.0101 \times 2^1$ +\end{itemize} + +\item We need not store the `1.' because {\em all} normalized floating +point numbers will start that way. Thus we can save memory when storing +normalized values by adding 1 to the significand. + +{ +\small +\setlength{\unitlength}{.15in} +\begin{picture}(32,4)(0,0) + \put(0,1){\line(1,0){32}} % bottom line + \put(0,2){\line(1,0){32}} % top line + + \put(0,1){\line(0,1){2}} % left vertical + \put(0,2){\makebox(1,1){\tiny 31}} % left end bit number marker + + \put(32,1){\line(0,1){2}} % vertical right end + \put(31,2){\makebox(1,1){\tiny 0}} % right end bit number marker + + \put(0,0){\makebox(1,1){\small sign}} + \put(1,0){\makebox(8,1){\small exponent}} + \put(9,0){\makebox(23,1){\small significand}} + + \put(0,1){\makebox(1,1){1}} % sign + + \put(1,1){\line(0,1){2}} % seperator + \put(1,2){\makebox(1,1){\tiny 30}} % bit marker + + \put(1,1){\makebox(1,1){1}} % exponent + \put(2,1){\makebox(1,1){0}} + \put(3,1){\makebox(1,1){0}} + \put(4,1){\makebox(1,1){0}} + \put(5,1){\makebox(1,1){0}} + \put(6,1){\makebox(1,1){0}} + \put(7,1){\makebox(1,1){0}} + \put(8,1){\makebox(1,1){0}} + + \put(8,2){\makebox(1,1){\tiny 23}} % bit marker + \put(9,1){\line(0,1){2}} % seperator + \put(9,2){\makebox(1,1){\tiny 22}} % bit marker + + \put(9,1){\makebox(1,1){0}} + \put(10,1){\makebox(1,1){1}} + \put(11,1){\makebox(1,1){0}} + \put(12,1){\makebox(1,1){1}} + \put(13,1){\makebox(1,1){0}} + \put(14,1){\makebox(1,1){0}} + \put(15,1){\makebox(1,1){0}} + \put(16,1){\makebox(1,1){0}} + \put(17,1){\makebox(1,1){0}} + \put(18,1){\makebox(1,1){0}} + \put(19,1){\makebox(1,1){0}} + \put(20,1){\makebox(1,1){0}} + \put(21,1){\makebox(1,1){0}} + \put(22,1){\makebox(1,1){0}} + \put(23,1){\makebox(1,1){0}} + \put(24,1){\makebox(1,1){0}} + \put(25,1){\makebox(1,1){0}} + \put(26,1){\makebox(1,1){0}} + \put(27,1){\makebox(1,1){0}} + \put(28,1){\makebox(1,1){0}} + \put(29,1){\makebox(1,1){0}} + \put(30,1){\makebox(1,1){0}} + \put(31,1){\makebox(1,1){0}} +\end{picture} +} + +%\item $-((1 + \frac{1}{4} + \frac{1}{16}) \times 2^{128-127}) = -(1 \frac{5}{16} \times 2^{1}) = -(1.3125 \times 2^{1}) = -2.625$ +\item $-((1 + \frac{1}{4} + \frac{1}{16}) \times 2^{128-127}) = -((1 + \frac{1}{4} + \frac{1}{16}) \times 2^1) = -(2 + \frac{1}{2} + \frac{1}{8}) = -(2 + .5 + .125) = -2.625$ + +\item IEEE754 formats: + +\begin{tabular}{|l|l|l|} +\hline + & IEEE754 32--bit & IEEE754 64--bit \\ +\hline +sign & 1 bit & 1 bit \\ +exponent & 8 bits (excess--127) & 11 bits (excess-1023) \\ +mantissa & 23 bits & 52 bits \\ +max exponent & 127 & 1023 \\ +min exponent & -126 & -1022 \\ +\hline +\end{tabular} + +\item When the exponent is all ones, the mantissa is all zeros, and +the sign is zero, the number represents positive infinity. + +\item When the exponent is all ones, the mantissa is all zeros, and +the sign is one, the number represents negative infinity. + +\item Note that the binary representation of an IEEE754 number in memory +can be compared for magnitude with another one using the same logic as for +comparing two's complement signed integers because the magnitude of an +IEEE number grows upward and downward in the same fashion as signed integers. +This is why we use excess notation and locate the significand's sign bit on +the left of the exponent. + +\item Note that zero is a special case number. Recall that a normalized +number has an implied 1--bit to the left of the significand\ldots\ which +means that there is no way to represent zero! +Zero is represented by an exponent of all--zeros and a significand of +all--zeros. This definition allows for a positive and a negative zero +if we observe that the sign can be either 1 or 0. + +\item On the number-line, numbers between zero and the smallest fraction in +either direction are in the {\em \gls{underflow}} areas. +\enote{Need to add the standard lecture numberline diagram showing +where the over/under--flow areas are and why.} + +\item On the number line, numbers greater than the mantissa of all--ones and the +largest exponent allowed are in the {\em \gls{overflow}} areas. + +\item Note that numbers have a higher resolution on the number--line when the +exponent is smaller. +\end{itemize} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Floating Point Number Accuracy} +Due to the finite number of bits used to store the value of a floating point +number, it is not possible to represent every one of the infinite values +on the real number line. The following C programs illustrate this point. + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsubsection{Powers Of Two} +Just like the integer numbers, the powers of two that have bits to represent +them can be represented perfectly\ldots\ as can their sums (provided that the +significand requires no more than 23 bits.) + +\listing{powersoftwo.c}{Precise Powers of Two} +\listing{powersoftwo.out}{Output from {\tt powersoftwo.c}} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsubsection{Clean Decimal Numbers} +When dealing with decimal values, you will find that they don't map simply +into binary floating point values. +% (the same holds true for binary integer numbers). + +Note how the decimal numbers are not accurately represented as they get larger. +The decimal number on line 10 of \listingRef{cleandecimal.out} +can be perfectly represented in IEEE format. However, a problem arises in +the 11Th loop iteration. It is due to the fact that the +binary number can not be represented accurately in IEEE format. Its least +significant bits were truncated in a best-effort attempt at rounding the value +off in order to fit the value into the bits provided. This is an example of +{\em low order truncation}. Once this happens, the value of \verb@x.f@ is +no longer as precise as it could be given more bits in which to save its value. + +\listing{cleandecimal.c}{Print Clean Decimal Numbers} +\listing{cleandecimal.out}{Output from {\tt cleandecimal.c}} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsubsection{Accumulation of Error} +These rounding errors can be exaggerated when the number we multiply +the \verb@x.f@ value by is, itself, something that can not be accurately +represented in IEEE +form.\footnote{Applications requiring accurate decimal values, such as +financial accounting systems, can use a packed--decimal numeric format +to avoid unexpected oddities caused by the use of binary numbers.} +\enote{In a lecture one would show that one tenth is a repeating +non--terminating binary number that gets truncated. This discussion +should be reproduced here in text form.} + +For example, if we multiply our \verb@x.f@ value by $\frac{1}{10}$ each time, +we can never be accurate and we start accumulating errors immediately. + +\listing{erroraccumulation.c}{Accumulation of Error} +\listing{erroraccumulation.out}{Output from {\tt erroraccumulation.c}} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Reducing Error Accumulation} +In order to use floating point numbers in a program without causing +excessive rounding problems an algorithm can be redesigned such that the +accumulation is eliminated. +This example is similar to the previous one, but this time we recalculate the +desired value from a known--accurate integer value. +Some rounding errors remain present, but they can not accumulate. + +\listing{errorcompensation.c}{Accumulation of Error} +\listing{errorcompensation.out}{Output from {\tt erroraccumulation.c}} diff --git a/book/numbers/cleandecimal.c b/book/numbers/cleandecimal.c new file mode 100644 index 0000000..2fe645a --- /dev/null +++ b/book/numbers/cleandecimal.c @@ -0,0 +1,22 @@ +#include +#include +#include + +union floatbin +{ + unsigned int i; + float f; +}; +int main() +{ + union floatbin x, y; + int i; + + x.f = 10; + while (x.f <= 10000000000000.0) + { + y.f = -x.f; + printf("%25.10f = %08x %25.10f = %08x\n", x.f, x.i, y.f, y.i); + x.f = x.f*10.0; + } +} diff --git a/book/numbers/cleandecimal.out b/book/numbers/cleandecimal.out new file mode 100644 index 0000000..12f1dc9 --- /dev/null +++ b/book/numbers/cleandecimal.out @@ -0,0 +1,13 @@ + 10.0000000000 = 41200000 -10.0000000000 = c1200000 + 100.0000000000 = 42c80000 -100.0000000000 = c2c80000 + 1000.0000000000 = 447a0000 -1000.0000000000 = c47a0000 + 10000.0000000000 = 461c4000 -10000.0000000000 = c61c4000 + 100000.0000000000 = 47c35000 -100000.0000000000 = c7c35000 + 1000000.0000000000 = 49742400 -1000000.0000000000 = c9742400 + 10000000.0000000000 = 4b189680 -10000000.0000000000 = cb189680 + 100000000.0000000000 = 4cbebc20 -100000000.0000000000 = ccbebc20 + 1000000000.0000000000 = 4e6e6b28 -1000000000.0000000000 = ce6e6b28 + 10000000000.0000000000 = 501502f9 -10000000000.0000000000 = d01502f9 + 99999997952.0000000000 = 51ba43b7 -99999997952.0000000000 = d1ba43b7 + 999999995904.0000000000 = 5368d4a5 -999999995904.0000000000 = d368d4a5 + 9999999827968.0000000000 = 551184e7 -9999999827968.0000000000 = d51184e7 diff --git a/book/numbers/erroraccumulation.c b/book/numbers/erroraccumulation.c new file mode 100644 index 0000000..6e4631a --- /dev/null +++ b/book/numbers/erroraccumulation.c @@ -0,0 +1,22 @@ +#include +#include +#include + +union floatbin +{ + unsigned int i; + float f; +}; +int main() +{ + union floatbin x, y; + int i; + + x.f = .1; + while (x.f <= 2.0) + { + y.f = -x.f; + printf("%25.10f = %08x %25.10f = %08x\n", x.f, x.i, y.f, y.i); + x.f += .1; + } +} diff --git a/book/numbers/erroraccumulation.out b/book/numbers/erroraccumulation.out new file mode 100644 index 0000000..0eebeca --- /dev/null +++ b/book/numbers/erroraccumulation.out @@ -0,0 +1,19 @@ +0.1000000015 = 3dcccccd -0.1000000015 = bdcccccd +0.2000000030 = 3e4ccccd -0.2000000030 = be4ccccd +0.3000000119 = 3e99999a -0.3000000119 = be99999a +0.4000000060 = 3ecccccd -0.4000000060 = becccccd +0.5000000000 = 3f000000 -0.5000000000 = bf000000 +0.6000000238 = 3f19999a -0.6000000238 = bf19999a +0.7000000477 = 3f333334 -0.7000000477 = bf333334 +0.8000000715 = 3f4cccce -0.8000000715 = bf4cccce +0.9000000954 = 3f666668 -0.9000000954 = bf666668 +1.0000001192 = 3f800001 -1.0000001192 = bf800001 +1.1000001431 = 3f8cccce -1.1000001431 = bf8cccce +1.2000001669 = 3f99999b -1.2000001669 = bf99999b +1.3000001907 = 3fa66668 -1.3000001907 = bfa66668 +1.4000002146 = 3fb33335 -1.4000002146 = bfb33335 +1.5000002384 = 3fc00002 -1.5000002384 = bfc00002 +1.6000002623 = 3fcccccf -1.6000002623 = bfcccccf +1.7000002861 = 3fd9999c -1.7000002861 = bfd9999c +1.8000003099 = 3fe66669 -1.8000003099 = bfe66669 +1.9000003338 = 3ff33336 -1.9000003338 = bff33336 diff --git a/book/numbers/errorcompensation.c b/book/numbers/errorcompensation.c new file mode 100644 index 0000000..544efb8 --- /dev/null +++ b/book/numbers/errorcompensation.c @@ -0,0 +1,24 @@ +#include +#include +#include + +union floatbin +{ + unsigned int i; + float f; +}; +int main() +{ + union floatbin x, y; + int i; + + i = 1; + while (i <= 20) + { + x.f = i/10.0; + y.f = -x.f; + printf("%25.10f = %08x %25.10f = %08x\n", x.f, x.i, y.f, y.i); + i++; + } + return(0); +} diff --git a/book/numbers/errorcompensation.out b/book/numbers/errorcompensation.out new file mode 100644 index 0000000..c83c1da --- /dev/null +++ b/book/numbers/errorcompensation.out @@ -0,0 +1,20 @@ +0.1000000015 = 3dcccccd -0.1000000015 = bdcccccd +0.2000000030 = 3e4ccccd -0.2000000030 = be4ccccd +0.3000000119 = 3e99999a -0.3000000119 = be99999a +0.4000000060 = 3ecccccd -0.4000000060 = becccccd +0.5000000000 = 3f000000 -0.5000000000 = bf000000 +0.6000000238 = 3f19999a -0.6000000238 = bf19999a +0.6999999881 = 3f333333 -0.6999999881 = bf333333 +0.8000000119 = 3f4ccccd -0.8000000119 = bf4ccccd +0.8999999762 = 3f666666 -0.8999999762 = bf666666 +1.0000000000 = 3f800000 -1.0000000000 = bf800000 +1.1000000238 = 3f8ccccd -1.1000000238 = bf8ccccd +1.2000000477 = 3f99999a -1.2000000477 = bf99999a +1.2999999523 = 3fa66666 -1.2999999523 = bfa66666 +1.3999999762 = 3fb33333 -1.3999999762 = bfb33333 +1.5000000000 = 3fc00000 -1.5000000000 = bfc00000 +1.6000000238 = 3fcccccd -1.6000000238 = bfcccccd +1.7000000477 = 3fd9999a -1.7000000477 = bfd9999a +1.7999999523 = 3fe66666 -1.7999999523 = bfe66666 +1.8999999762 = 3ff33333 -1.8999999762 = bff33333 +2.0000000000 = 40000000 -2.0000000000 = c0000000 diff --git a/book/numbers/powersoftwo.c b/book/numbers/powersoftwo.c new file mode 100644 index 0000000..30ca805 --- /dev/null +++ b/book/numbers/powersoftwo.c @@ -0,0 +1,22 @@ +#include +#include +#include + +union floatbin +{ + unsigned int i; + float f; +}; +int main() +{ + union floatbin x; + union floatbin y; + int i; + x.f = 1.0; + while (x.f > 1.0/1024.0) + { + y.f = -x.f; + printf("%25.10f = %08x %25.10f = %08x\n", x.f, x.i, y.f, y.i); + x.f = x.f/2.0; + } +} diff --git a/book/numbers/powersoftwo.out b/book/numbers/powersoftwo.out new file mode 100644 index 0000000..e24f79c --- /dev/null +++ b/book/numbers/powersoftwo.out @@ -0,0 +1,10 @@ +1.0000000000 = 3f800000 -1.0000000000 = bf800000 +0.5000000000 = 3f000000 -0.5000000000 = bf000000 +0.2500000000 = 3e800000 -0.2500000000 = be800000 +0.1250000000 = 3e000000 -0.1250000000 = be000000 +0.0625000000 = 3d800000 -0.0625000000 = bd800000 +0.0312500000 = 3d000000 -0.0312500000 = bd000000 +0.0156250000 = 3c800000 -0.0156250000 = bc800000 +0.0078125000 = 3c000000 -0.0078125000 = bc000000 +0.0039062500 = 3b800000 -0.0039062500 = bb800000 +0.0019531250 = 3b000000 -0.0019531250 = bb000000 diff --git a/book/preamble.tex b/book/preamble.tex new file mode 100644 index 0000000..7ddca66 --- /dev/null +++ b/book/preamble.tex @@ -0,0 +1,261 @@ + +\oddsidemargin=.82in +\evensidemargin=1.82in + +%\topmargin=-.5in +\headheight=12pt +\headsep=20pt + +\hoffset=-1.2in % for 8.5x11 +%\voffset=-1.15in % for 8.5x11 +\voffset=-.8in % for 8.5x11 +%\textheight=9.75in % for 8.5x11 +\textheight=9in % for 8.5x11 +%\textheight=8.75in % for 8.5x11 + +%\textwidth=348pt % for 8.5x11 +%\textwidth=6in % for 8.5x11 +\textwidth=6.25in % for 8.5x11 + +\marginparsep=7pt +%\marginparwidth=71pt +%\marginparwidth=1.25in +%\marginparwidth=1.5in +\marginparwidth=1.25in +\footskip=36pt +\marginparpush=5pt + + +\usepackage{ifthen} +\usepackage{stringstrings} % so can count characters in a string +\usepackage{xstring} % so can count characters in a string + +\usepackage[pass]{geometry} +\usepackage{color} % Necessary for colored links + +% load makeidx BEFORE hyperref to make the index clickable +% load makeidx AFTER hyperref if want to use showidx +%\usepackage{makeidx} +\usepackage[pagebackref]{hyperref} +\hypersetup{ + colorlinks=true, %set true if you want colored links + linkcolor=blue %choose some color if you want links to stand out +} + +\usepackage{makeidx,showidx} % showidx breaks hyperref when loaded before hyperref + + + +%\usepackage{url} + +\usepackage{lastpage} +\usepackage{fancyhdr} + +\usepackage{amsmath} +\numberwithin{equation}{section} +\usepackage{amsfonts} % I hear these are also good to load +\usepackage{amssymb} % I hear these are also good to load + +%\usepackage{picture} +%\usepackage{epstopdf} +%\usepackage{graphicx} +\usepackage{epsfig} +\usepackage{tikz-timing} +\usepackage{tikz} +%\usepackage{timing} +\usepackage{float} +\usepackage{fancyvrb} +\usepackage{caption} +\usepackage{placeins} + +\usepackage{listings} + +\usepackage[toc]{glossaries} +%\renewcommand*{\glsclearpage}{} + +\usepackage{pifont} +\usepackage{layout} + +\usepackage{xcolor} +\usepackage{textcomp} % for the trademark symbol + +%\usepackage[obeyspaces]{url} +\usepackage{fink} % deprecated in favor of currfile +%\usepackage{currfile} % dut... doesn't emit the local include path properly + +\usepackage{MyFigs} + +\def\code#1{\url{#1}} + +% The exercise environment +\usepackage{exercise} + +\renewcommand{\ExerciseHeader}{% +\textbf{\large\ExerciseHeaderDifficulty\ExerciseName\ % +\ExerciseHeaderNB\ExerciseHeaderTitle\ExerciseHeaderOrigin}\medskip} + +\renewcommand{\ExePartHeader}{% +\medskip\emph{\large\ExePartHeaderDifficulty\ExePartName % +\ExePartHeaderNB \ExePartHeaderTitle\\ +}} + +%\renewcommand{\ExePartHeader}{% +%\medskip\emph{\large\ExePartHeaderDifficulty Part \ExePartHeaderNB % +%\quad \ExePartName\ExePartHeaderTitle}} + + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%\DefineVerbatimEnvironment% +%{Code}{Verbatim} +%{frame=single,numbers=left,numbersep=2mm,framesep=3mm} +%%%,numbersep=2mm,frame=lines,framerule=0.8mm,framesep=5mm + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% [1] = filename to include +% [2] = title of the code sample +% A label will be generated as: Code:#1 +%\newcommand{\xxxx}[2]{% +% \label{Code:#1} % +% \VerbatimInput[frame=single,numbers=left,numbersep=2mm,framesep=3mm,label={#2}]{#1}} + +\newcommand{\theListingFontFamily}{\ttfamily\small} +%\newcommand{\theListingFontFamily}{\ttfamily\footnotesize} +%\newcommand{\theListingFontFamily}{\ttfamily\scriptsize} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% [1] = place for additional listing parameters, default: language=C +% [2] = filepath +% [3] = Description of the listing +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\newcommand{\listing}[3][language=C]{% + \lstinputlisting[ % + numbers=left,numberstyle=\tiny,stepnumber=1,numbersep=8pt, % + breaklines=true, % + frame=single % + showtabs=false, % + basicstyle=\theListingFontFamily, % + showstringspaces=false, % + tabsize=4, % + showlines=true, % show all blank lines + #1, % + captionpos=t,frame=tblr,label={lst:\detokenize{#2}},caption={{\tt \detokenize{#2}}\\\hspace{\textwidth}{\small #3}}]{\detokenize{#2}}} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\newcommand{\listingRef}[1]{\autoref{lst:\detokenize{#1}}} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\lstnewenvironment{tty} + {\lstset{language=sh, % + numbers=left,numberstyle=\tiny,stepnumber=1,numbersep=8pt, % + breaklines=true, % + frame=l, % + showtabs=false, % + basicstyle=\theListingFontFamily, % + showstringspaces=false, % + tabsize=4, % + showlines=true, % show all blank lines + basicstyle=\theListingFontFamily}} + {} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% A footer that shall appear on every page + +%\newcommand{\MyFoot}{{\sf\scriptsize Copyright \copyright\ 2014, 2015 John Winans. All Rights Reserved}\\ +%\vspace{.05in} +%\scriptsize\FooterText} + +\newcommand{\MyFoot}{\scriptsize\FooterText} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\pagestyle{fancy} + +% supress normal headings and footers +\fancyhf{} + +% heading and footing rules +\renewcommand{\headrulewidth}{1pt} +\renewcommand{\footrulewidth}{1pt} + + +%\def\DiscardOneCharacter#1{} +% Sub-footer that shows the version control version string in the lfoot defined above +\ifdefined\GitFileName +% \newcommand{\FooterText}{\tt \GitFileName \currfilename\\ + \newcommand{\FooterText}{\tt \GitFileName \finkpath\\ +\GitDescription} +\else + \newcommand{\FooterText}{\emph{--UNKNOWN--}} +\fi + +%\lhead{\leftmark} +%\rhead{\rightmark} +\fancyhead[LE]{\leftmark} +\fancyhead[RO]{\rightmark} + +\newcommand{\PageNumber}{Page \thepage\ of \pageref*{LastPage}} +%\rfoot{Page \thepage\ of \pageref{LastPage}} +%\lfoot{\MyFoot} + +\fancyfoot[LE,RO]{\PageNumber} +\fancyfoot[RE,LO]{\MyFoot} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% override the plain page style so the first page of a +% chapter still has a footer on it (but no header). + +\fancypagestyle{plain}{% +\renewcommand{\headrulewidth}{0pt} % +\fancyhf{} % clear all header and footer fields +\fancyfoot[LE,RO]{\PageNumber} +\fancyfoot[RE,LO]{\MyFoot} +%\lfoot{\MyFoot} % +%\rfoot{Page \thepage\ of \pageref*{LastPage}} +} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\setlength{\parindent}{0pt} +\setlength{\parskip}{.51em} + +% How deep should we enumerate the section/subsection/subsubsections +% 3=all the way +\setcounter{secnumdepth}{3} + +% How many section-levels to show in the TOC. +% 4=all of them +\setcounter{tocdepth}{4} +%\setcounter{tocdepth}{1} + + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% Presentation styles for things like names links and +% window objects in figures. + +% how should we present a window name +\newcommand{\windowname}[1]{{\em #1}} + +% How should we present the name of an object in a figure +% that can be interacted with. +\newcommand{\linkname}[1]{{\bf #1}} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% fix some annoying things + +\newcommand{\tm}{\textsuperscript{TM}} +\newcommand{\rtm}{\textsuperscript{\textregistered}} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% A command to make a colored background box whilst in math mode: +\newcommand{\MathHilight}[1]{\colorbox{yellow}{\ensuremath{#1}}} + +\usepackage{tcolorbox} +%\tcbset{colback=blue!20!white} +\tcbset{colback=green!20!white} + diff --git a/book/preface/chapter.tex b/book/preface/chapter.tex new file mode 100644 index 0000000..7a9268a --- /dev/null +++ b/book/preface/chapter.tex @@ -0,0 +1,49 @@ +\chapter{Preface} +\label{chapter:Preface} + +I set out to this book because I couldn't find it in a single volume elsewhere. + +The closest thing to what I sought when deciding to collect my thoughts +into this document would be select portions of +{\em The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 2.2}\cite{rvismv1v22:2017}, +{The RISC-V Reader}\cite{riscvreader:2017}, and +{Computer Organization and Design RISC-V Edition: The Hardware Software Interface}\cite{codriscv:2017}. + +There {\em are} some terse guides around the Internet that are suitable +for those that already know an assembly language. With all the (deserved) +excitement brewing over system organization (and the need to compress the +time out of university courses targeting assembly language +programming~\cite{Decker:1985:MAT:989369.989375}), +it is no surprise that RISC-V texts for the beginning assembly programmer +are not (yet) available. + +When I got started in computing I learned how to count in binary +in a high school electronics course using data sheets for integrated +circuits such as the 74191\cite{ttl74191:1979} and 74154\cite{ttl74154:1979} +prior to knowing that assembly language even existed. + +I learned assembler from data sheets and texts (that are still sitting on +my shelves) such as: +\begin{itemize} +\item The MCS-85 User's Manual\cite{mcs85:1978} +\item The EDTASM Manual\cite{edtasm:1978} +\item The MC68000 User's Manual\cite{mc68000:1980} +\item Assembler Language With ASSIST\cite{assist:1983} +\item IBM System/370 Principals of Operation\cite{poo:1980} +\item OS/VS-DOS/VSE-VM/370 Assembler Language\cite{assembler370:1979} +%\item The Series 32000 Databook\cite{ns32k:1986} +\item \ldots\ and several others +\end{itemize} + +One way or another all of them discuss each CPU instruction in excruciating detail +with both a logical and narrative description. For RISC--V this is +also the case for the {\em RISC-V Reader}\cite{riscvreader:2017} and the +{\em Computer Organization and Design RISC-V Edition}\cite{codriscv:2017} books +and is also present in this text (I consider that to be the minimal +level of responsibility.) + +Where I hope this text will differentiate itself from the existing RISC-V +titles is in its attempt to address the needs of those learning assembly +language for the first time. To this end I have primed this project with +some of the material from old handouts I used when teaching assembly language +programming in the late '80s. diff --git a/book/rv32/chapter.tex b/book/rv32/chapter.tex new file mode 100644 index 0000000..aadb46e --- /dev/null +++ b/book/rv32/chapter.tex @@ -0,0 +1,1688 @@ +\chapter{RV32 Machine Instructions} +\label{chapter:RV32} +\index{RV32} + +\section{Introduction} + +\enote{Discuss what the IMAFD, G and other ISA extensions mean as well as the +32, 64 and 128--bit versions.} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\section{Conventions and Terminology} + +When discussing instructions, the following abbreviations/notations are used: + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{XLEN} + +XLEN represents the bit--length of an \reg{x} register in the machine architecture. +Possible values are 32, 64 and 128. + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{sx(val)} +\label{extension:sx} + +Sign extend {\em val} to the left. + +This is used to convert a signed integer value expressed using some number of +bits to a larger number of bits by adding more bits to the left. In doing so, +the sign will be preserved. In this case {\em val} represents the least +\acrshort{msb}s of the value. +For more on binary numbers see \autoref{chapter:NumberSystems}. + +\autoref{Figure:SignExtendNegative} illustrates extending the negative sign +bit of {\em val} to the left by replicating it. +When {\em val} is negative, its \acrshort{msb} (bit 19 in this example) will +be set to 1. Extending this value to the left will set all the new bits +to the left of it to 1 as well. + + +\begin{figure}[ht] +\centering +\DrawBitBoxSignExtendedPicture{32}{10100000000000000010} +\captionof{figure}{Sign--extending a negative integer from 20 bits to 32 bits.} +\label{Figure:SignExtendNegative} +\end{figure} + + +\autoref{Figure:SignExtendPositive} illustrates extending the positive sign +bit of {\em val} to the left by replicating it. +When {\em val} is positive, its \acrshort{msb} will be set to 0. Extending this +value to the left will set all the new bits to the left of it to 0 as well. + + +\begin{figure}[ht] +\centering +\DrawBitBoxSignExtendedPicture{32}{01000000000000000010} +\captionof{figure}{Sign--extending a positive integer from 20 bits to 32 bits.} +\label{Figure:SignExtendPositive} +\end{figure} + + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{zx(val)} +\label{extension:zx} + +Zero extend {\em val} to the left. + +This is used to convert an unsigned integer value expressed using some number of +bits to a larger number of bits by adding more bits to the left. In doing so, +the new bits added will all be set to zero. As is the case with \verb@sx(val)@, +{\em val} represents the \acrshort{lsb}s of the final value. +\autoref{Figure:ZeroExtend} illustrates zero--extending a 20--bit {\em val} to the +left to form a 32--bit fullword. + +For more on binary numbers see \autoref{chapter:NumberSystems}. + +\begin{figure}[ht] +\centering +\DrawBitBoxZeroExtendedPicture{32}{10000000000000000010} +\captionof{figure}{Zero--extending an unsigned integer from 20 bits to 32 bits.} +\label{Figure:ZeroExtend} +\end{figure} + + + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{zr(val)} +\label{extension:zr} + +Zero extend {\em val} to the right. + +Some times a binary value is encoded such that a set of bits represented +by {\em val} are used to represent the \acrshort{msb}s of some longer (more bits) +value. +In this case it is necessary to append zeroes to the right to convert \verb@val@ to +the longer value. + +\autoref{Figure:ZeroRightExtend} illustrates converting a 20--bit {\em val} to +a 32--bit fullword. + +\begin{figure}[ht] +\centering +\DrawBitBoxSignLeftZeroRightExtendedPicture{32}{01000000000000000010}{12} +\captionof{figure}{Zero--extending an integer to the right from 20 bits to 32 bits.} +\label{Figure:ZeroRightExtend} +\end{figure} + +%\begin{figure}[ht] +%\centering +%\parbox{.7\linewidth}{ +%\DrawBitBoxUnsignedPicture{01000000000000000010}\\ +%\DrawBitBoxUnsignedPicture{01000000000000000010000000000000} +%} +%\captionof{figure}{Zero--extending an integer to the right from 20 bits to 32 bits.} +%\label{Figure:ZeroRightExtend} +%\end{figure} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Sign Entended Left and Zero Extend Right} +\label{extension:slzr} + +Some instructions such as the J--type (see \autoref{insnformat:jtype}) include +immediate operands that are extended in both directions. + +\autoref{Figure:slzrPositive} and \autoref{Figure:slzrNegative} +illustrates zero--extending a 20--bit negative number one bit to the right +and sign--extending it 11 bits to the left: + +\begin{figure}[ht] +\centering +\DrawBitBoxSignLeftZeroRightExtendedPicture{32}{01000100011101001001}{1} +\captionof{figure}{Sign--extending a positive 20--bit number +11 bits to the left and one bit to the right.} +\label{Figure:slzrPositive} +\end{figure} + +\begin{figure}[ht] +\centering +\DrawBitBoxSignLeftZeroRightExtendedPicture{32}{11000100011101001001}{1} +\captionof{figure}{Sign--extending a negative 20--bit number +11 bits to the left and one bit to the right.} +\label{Figure:slzrNegative} +\end{figure} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{m8(addr)} +\label{memory:m8} + +The contents of an 8--bit value in memory at address {\em addr}. + +Given the contents of the memory dump shown in +\autoref{Figure:SampleMemoryContents}, +\verb@m8(42)@ refers to the memory location at address \verb@42@$_{16}$ +that currently contains the 8--bit value \verb@fc@$_{16}$. + +The \verb@mn(addr)@ notation can be used to refer to memory that is being +read or written depending on the context. + +When memory is being written, the following notation is used to indicate that +the least significant 8 bis of {\em source} will be is written into memory at +the address {\em addr}: + +\verb@m8(addr)@ $\leftarrow$ \verb@source@ + +When memory is being read, the following notation is used to indicate that the +8 bit value at the address {\em addr} will be read and stored into {\em dest}: + +\verb@dest@ $\leftarrow$ \verb@m8(addr)@ + +Note that {\em source} and {\em dest} are typically registers. + + +\begin{figure}[ht] +\centering +\begin{BVerbatim} + + +00000030 2f 20 72 65 61 64 20 61 20 62 69 6e 61 72 79 20 +00000040 66 69 fc 65 20 66 69 6c 6c 65 64 20 77 69 74 68 +00000050 20 72 76 33 32 49 20 69 6e 73 74 72 75 63 74 69 +00000060 6f 6e 73 20 61 6e 64 20 66 65 65 64 20 74 68 65 +\end{BVerbatim} +\captionof{figure}{Sample memory contents.} +\label{Figure:SampleMemoryContents} +\end{figure} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{m16(addr)} + +The contents of an 16--bit little--endian value in memory at address {\em addr}. + +Given the contents of the memory dump shown in +\autoref{Figure:SampleMemoryContents}, +\verb@m16(42)@ refers to the memory location at address \verb@42@$_{16}$ +that currently contains \verb@65fc@$_{16}$. See also~\autoref{memory:m8}. + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{m32(addr)} + +The contents of an 32--bit little--endian value in memory at address {\em addr}. + +Given the contents of the memory dump shown in +\autoref{Figure:SampleMemoryContents}, +\verb@m32(42)@ refers to the memory location at address \verb@42@$_{16}$ +that currently contains \verb@662065fc@$_{16}$. +See also~\autoref{memory:m8}. + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{m64(addr)} + +The contents of an 64--bit little--endian value in memory at address {\em addr}. + +Given the contents of the memory dump shown in +\autoref{Figure:SampleMemoryContents}, +\verb@m64(42)@ refers to the memory location at address \verb@42@$_{16}$ +that currently contains \verb@656c6c69662065fc@$_{16}$. +See also~\autoref{memory:m8}. + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{m128(addr)} + +The contents of an 128--bit little--endian value in memory at +address {\em addr}. + +Given the contents of the memory dump shown in +\autoref{Figure:SampleMemoryContents}, +\verb@m128(42)@ refers to the memory location at address \verb@42@$_{16}$ +that currently contains \verb@7220687469772064656c6c69662065fc@$_{16}$. +See also~\autoref{memory:m8}. + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{.+offset} + +The address of the current instruction plus a numeric offset. + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{.-offset} + +The address of the current instruction minus a numeric offset. + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{pc} + +The current value of the program counter. + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{rd} + +An x--register used to store the result of instruction. + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{rs1} + +An x--register value used as a source operand for an instruction. + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{rs2} + +An x--register value used as a source operand for an instruction. + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{imm} + +An immediate numeric operand. The word {\em immediate} refers +to the fact that the operand is stored within an instruction. + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{rsN[h:l]} + +The value of bits from {\em h} through {\em l} of x--register rsN. +For example: rs1[15:0] refers to the contents of +the 16 \acrshort{lsb}s of rs1. + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\section{Addressing Modes} + +immediate, register, base-displacement, pc-relative +\enote{Write this section.} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\section{Instruction Encoding Formats} +\label{section:EncodingFormats} + +This +\enote{Should discuss types and sizes beyond the fundamentals. Will add +if/when instruction details are added in the future.} +document concerns itself with the following RISC-V instruction formats. + +XXX Show and discuss a stack of formats explaining how the unnatural ordering +of the {\em imm} fields reduces the number of possible locations that +the hardware has to be prepared to {\em look} for various bits. For example, +the opcode, rd, rs1, rs1, func3 and the sign bit (when used) are all always +in the same position. Also note that imm[19:12] and imm[10:5] can only be +found in one place. imm[4:0] can only be found in one of two places\ldots + +The point to all this is that it is easier to build a machine if it +does not have to accommodate many different ways to perform the same task. +This simplification can also allow it operate faster. + +\autoref{Figure:riscvFormats} Shows the RISC-V instruction formats. + +\begin{figure}[ht] +\DrawInsnTypeBTikz{00000000000000000000000000000000}\\ +\DrawInsnTypeUTikz{00000000000000000000000000000000}\\ +\DrawInsnTypeJTikz{00000000000000000000000000000000}\\ +\DrawInsnTypeITikz{00000000000000000000000000000000}\\ +\DrawInsnTypeSTikz{00000000000000000000000000000000}\\ +\DrawInsnTypeRShiftTikz{00000000000000000000000000000000}\\ +\DrawInsnTypeRTikz{00000000000000000000000000000000} +\captionof{figure}{RISC-V instruction formats.} +\label{Figure:riscvFormats} +\end{figure} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{U Type} +\label{insnformat:utype} + +The U--Type format is used for instructions that use a 20--bit immediate operand +and a destination register. + +\DrawInsnTypeUTikz{11010110000000000011001010110111} + +The \reg{rd} field contains an \reg{x} register number to be set to a value that +depends on the instruction. + +The imm field +contains a 20--bit value that will be converted into \Gls{xlen} bits by +using the {\em imm} operand for bits 31:12 and then sign-extending it +to the left\footnote{When XLEN is larger than 32.} and zero--extending +the LSBs as discussed in \autoref{extension:zr}. + +If \Gls{xlen}=32 then the imm value in this example will be +converted as shown below. + +\DrawBitBoxSignLeftZeroRightExtendedPicture{32}{11010110000000000011}{12} + +Notice that the 20--bits of the imm field are mapped in the same order and +in the same relative position that they appear in the instruction when +they are used to create the value of the immediate operand. +Shifting the imm value to the left, into the ``upper bits'' of the immediate +value suggests a rationale for the name of this format. + +%from $01010110000000000011_2$ (\verb@d6003@$_{16}$) to +%$11010110000000000011000000000000_2$ (\verb@d6003000@$_{16}$). + +If \Gls{xlen}=64 then the imm value in this example will be converted to the +same two's complement integer value by extending the sign to the left. + +%\DrawBitBoxSignLeftZeroRightExtendedPicture{64}{11010110000000000011}{12} +%$1111111111111111111111111111111111010110000000000011000000000000_2$ +%(\verb@ffffffffd6003000@$_{16}$). + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{J Type} +\label{insnformat:jtype} + +The J--type format is used for instructions that use a 20--bit immediate operand +and a destination register. It is similar to the U--type. However, the immediate +operand is constructed by arranging the {\em imm} bits in a different manner. + +\DrawInsnTypeJTikz{00111001001110000001001111101111} + +The \reg{rd} field contains an \reg{x} register number to be set to a value that +depends on the instruction. + + +In the J--type format the 20 {\em imm} bits are arranged such +that they represent the ``lower'' portion of the immediate value. Unlike +the U--type +instructions, the J-type requires the bits to be re--ordered and shifted +to the right before they are used.\footnote{The reason that the J--type +bits are reordered like this is because it simplifies the implementation of +hardware as discussed in \autoref{section:EncodingFormats}.} + +The example above shows that the bit positions in the {\em imm} field +description. We see that the 20 {\em imm} bits are re--ordered according to: +[20\textbar10:1\textbar11\textbar19:12]. +This means that the \acrshort{msb} of the {\em imm} field is to be placed +into bit 20 of the immediate integer value ultimately used by the instruction +when it is converted into \Gls{xlen} bits. +The next bit to the right in the {\em imm} field is to be placed into bit 10 of +the immediate value and so on. + +After the {\em imm} bits are re-positioned into bits 20:1 of the immediate value +being constructed, a zero--bit will be added to the \acrshort{lsb} +and the value in bit--position 20 will be replicated to sign--extend the +value to \Gls{xlen} bits as discussed in \autoref{extension:slzr}. + +If \Gls{xlen}=32 then the {\em imm} value in this example will be converted as +shown below. + +\DrawBitBoxSignLeftZeroRightExtendedPicture{32}{01000000110111001001}{1} + +%$00111001001110000001_2$ (\verb@39381@$_16$) to +%$00000000000010000001101110010010_2$ (\verb@00081b92@$_16$). +% +%If \Gls{xlen}=64 then the imm value in this example will be converted to\\ +%$0000000000000000000000000000000000000000000010000001101110010010_2$ +%(\verb@0000000000081b92@$_16$). + +A J--type example with a negative imm field: + +\DrawInsnTypeJTikz{10111001001110000001001111101111} + +If \Gls{xlen}=32 then the {\em imm} field in this example will be converted as +shown below. + +\DrawBitBoxSignLeftZeroRightExtendedPicture{32}{11000000110111001001}{1} + +%$10111001001110000001_2$ (\verb@b9381@$_16$) to +%$1111111111111000 0001101110010010_2$ (\verb@fff81b92@$_16$). +% +%If \Gls{xlen}=32 then the imm value in this example will be converted to +%\verb@fffffffffff81b92@$_16$. + +The J--type format is used by the Jump And Link instruction that calculates +a target address by adding a signed immediate value to the current program +counter. Since no instruction can be placed at an odd address the 20--bit +imm value is zero--extended to the right to represent a 21-bit signed offset +capable of representing numbers twice the magnitude of the 20--bit imm value. + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{R Type} +\label{insnformat:rtype} +\DrawInsnTypeRTikz{01000001111100011000001110110011} + +A special case of the R-type used for shift--immediate instructions where +the {\em rs2} field is used as an immediate value named {\em shamt} +representing the number of bit positions to shift: + +\DrawInsnTypeRShiftTikz{00000000001000011001001110100011} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{I Type} +\label{insnformat:itype} +\DrawInsnTypeITikz{00000000010000011000001110000011} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{S Type} +\label{insnformat:stype} +\DrawInsnTypeSTikz{00000000111100011000100110100011} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{B Type} +\label{insnformat:btype} +\DrawInsnTypeBTikz{00000000111100011000100011100011} + +%insnTypeF +%insnTypeCSRR + + + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{CPU Registers} +\label{cpuregs} + +The registers are names x0 through x31 and have aliases suited to their +conventional use. The following table describes each register. + +Note +\enote{Need to add a section that discusses the calling conventions} +that the calling calling convention specifies that only some +of the registers are to be saved by functions if they alter their contents. +The idea being that accessing memory is time-consuming and that by +classifying some registers as ``temporary'' (not saved by any function +that alter its contents) it is possible to carefully implement a function +with less need to store register values on the stack in order to use them +to perform the operations of the fuction. + +The lack of grouping the temporary and saved registers is due to the +fact that the C extension %See \autoref{rv32:c} +provides access to only the first 16 registers when executing instructions +in the compressed format. + + +\begin{center} +\begin{tabular}{|l|l|l|l|} +\hline +Reg & Alias & Description & Saved \\ +\hline +\hline +x0 & zero & Hard-wired zero & \\ +x1 & ra & Return address & \\ +x2 & sp & Stack pointer & yes \\ +x3 & gp & Global pointer & \\ +x4 & tp & Thread pointer & \\ +x5 & t0 & Temporary/alternate link register & \\ +x6 & t1 & Temporary & \\ +x7 & t2 & Temporary & \\ +x8 & s0/fp & Saved register/frame pointer & yes \\ +x9 & s1 & Saved register & yes \\ +x10 & a0 & Function argument/return value & \\ +x11 & a1 & Function argument/return value & \\ +x12 & a2 & Function argument & \\ +x13 & a3 & Function argument & \\ +x14 & a4 & Function argument & \\ +x15 & a5 & Function argument & \\ +x16 & a6 & Function argument & \\ +x17 & a7 & Function argument & \\ +x18 & s2 & Saved register & yes \\ +x19 & s3 & Saved register & yes \\ +x20 & s4 & Saved register & yes \\ +x21 & s5 & Saved register & yes \\ +x22 & s6 & Saved register & yes \\ +x23 & s7 & Saved register & yes \\ +x24 & s8 & Saved register & yes \\ +x25 & s9 & Saved register & yes \\ +x26 & s10 & Saved register & yes \\ +x27 & s11 & Saved register & yes \\ +x28 & t3 & Temporary & \\ +x29 & t4 & Temporary & \\ +x30 & t5 & Temporary & \\ +x31 & t6 & Temporary & \\ +\hline +\end{tabular} +\end{center} + + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\section{memory} + +Note that RISC-V is a little-endian machine. + +All instructions must be naturally aligned to their 4--byte +boundaries.~\cite[p.~5]{rvismv1v22:2017} + +If a RISC-V processor implements the C (compressed) extension then +instructions may be aligned to 2--byte +boundaries.\cite[p.~68]{rvismv1v22:2017} + +Data alignment is not necessary but unaligned data can be inefficient. +Accessing unaligned data using any of the load or store instructions can +also prevent a mempry access from operating +atomically.~\cite[p.19]{rvismv1v22:2017} See also \autoref{RV32A}. + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\section{RV32I Base Instruction Set} +\index{RV32I} + +\Gls{rv32}I refers to the basic 32-bit integer instructions. + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{LUI rd, imm} +\index{Instruction!LUI} + +Load Upper Immediate. + +\verb@rd@ $\leftarrow$ \verb@zr(imm)@ + +Copy the immediate value into bits 31:12 of the destination register and +place zeroes into bits 11:0. +When XLEN is 64 or 128, the immediate value is sign--extended to the left. + +Instruction Format and Example: + +\textbf{\large LUI t0, 3}\\ +\DrawInsnTypeUPicture{LUI t0, 3}{00000000000000000011001010110111} + +t0 = 0x00000300 + +\textbf{\large LUI t0, -1}\\ +\DrawInsnTypeUPicture{LUI t0, 3}{11111111111111111111001010110111} + +t0 = 0xfffff000 + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{AUIPC rd, imm} +\index{Instruction!AUIPC} + +Add Upper Immediate to PC. + +\verb@rd@ $\leftarrow$ \verb@pc + zr(imm)@ + +Create a signed 32--bit value by zero--extending imm[31:12] to the +right (see \autoref{extension:zr}) and add this value to the +\reg{pc} register, placing the result into \reg{rd}. + +When XLEN is 64 or 128, the value placed into \reg{rd} will be +sign--extended to the left. + + +Encoding: + +\textbf{\large AUIPC t0, 3}\\ +\DrawInsnTypeUPicture{AUIPC t0, 3}{00000000000000000011001010110111} + +State of registers before execution: + +pc = 0x11114444 + +Decoding the instruction: + +op-code = 0110111\\ +rd = x5\\ +imm = 0x00003000 + +After execution: + +pc = 0x11114444\\ +x5 = 0x11117444 + +The AUIPC instruction supports two-instruction sequences to access arbitrary +offsets from the PC for both control-flow transfers and data accesses. +The combination of an AUIPC and the 12-bit immediate in a JALR can transfer +control to any 32-bit PC-relative address, while an AUIPC plus the 12-bit +immediate offset in regular load or store instructions can access any 32-bit +PC-relative data address.~\cite[p.~14]{rvismv1v22:2017} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{JAL rd, imm} +\index{Instruction!JAL} + +Jump and link. + +\verb@rd@ $\leftarrow$ \verb@pc + 4@\\ +\verb@pc@ $\leftarrow$ \verb@pc + sx(imm<<1)@ + +This instruction saves the address of the next instruction +that would otherwise execute (located at \reg{pc}+4) into +\reg{rd} and then adds immediate value to the \reg{pc} causing +an unconditional branch to take place. + +The standard software conventions for calling subroutines +use \reg{x1} as the return address (\reg{rd} register in this +case).~\cite[p.~16]{rvismv1v22:2017} + + +Encoding: + +\DrawInsnTypeJPicture{JAL x7, .+16}{00000001000000000000001111101111} + +imm demultiplexed value = $00000000000000001000_2 \ll 1 = 16_{10}$ + + +State of registers before execution: + +pc = 0x11114444 + +State of registers after execution: + +pc = 0x11114454 +x7 = 0x11114448 + +JAL provides a method to call a subroutine using a pc-relative address. + + +\DrawInsnTypeJPicture{JAL x7, .-16}{11111111000111111111001111101111} + +imm demultiplexed value = $11111111111111111000_2 \ll 1 = -16_{10}$ + +State of registers before execution: + +pc = 0x11114444 + +State of registers after execution: + +pc = 0x11114434 +x7 = 0x11114448 + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{JALR rd, rs1, imm} +\index{Instruction!JALR} + +Jump and link register. + +\verb@rd@ $\leftarrow$ \verb@pc + 4@\\ +\verb@pc@ $\leftarrow$ \verb@(rs1 + sx(imm)) & ~1@ + +This instruction saves the address of the next instruction +that would otherwise execute (located at \reg{pc}+4) into +\reg{rd} and then adds the immediate value to the \reg{rs1} +register and stores the sum into the \reg{pc} register causing +an unconditional branch to take place. + +Note that the branch target address is calculated by +sign--extending the imm[11:0] bits from the instruction, +adding it to the \reg{rs1} register and {\em then} the +LSB of the sum is to zero and the result is stored into the +\reg{pc} register. +The discarding of the LSB allows the branch to refer to any +even address. + +The standard software conventions for calling subroutines +use \reg{x1} as the return address (\reg{rd} register in this +case).~\cite[p.~16]{rvismv1v22:2017} + + +Encoding: + +\DrawInsnTypeIPicture{JALR x1, x7, 4}{00000000010000111000000011100111} + +Before: + +pc = 0x11114444\\ +x7 = 0x44444444 + +After + +pc = 0x5555888c\\ +x1 = 0x11114448 + +JALR provides a method to call a subroutine using a base-displacement address. + +\DrawInsnTypeIPicture{JALR x1, x0, 5}{00000000010100000000000011100111} + +Note that the least significant bit in the result of rs1+imm is +discarded/set to zero before the result is saved in the pc. + +pc = 0x11114444 + +After + +pc = 0x00000004\\ +x1 = 0x11114448 + + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{BEQ rs1, rs2, imm} +\index{Instruction!BEQ} + +Branch if equal. + +\verb@pc@ $\leftarrow$ \verb@(rs1 == rs2) ? pc+sx(imm[12:1]<<1) : pc+4@ + +Encoding: + +\DrawInsnTypeBPicture{BEQ x3, x15, 2064}{00000000111100011000100011100011} + +imm[12:1] = $010000001000_2 = 1032_{10}$\\ +imm = $2064_{10}$\\ +funct3 = $000_2$\\ +rs1 = x3\\ +rs2 = x15 + + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{BNE rs1, rs2, imm} +\index{Instruction!BNE} + +Branch if Not Equal. + +\verb@pc@ $\leftarrow$ \verb@(rs1 != rs2) ? pc+sx(imm[12:1]<<1) : pc+4@ + +Encoding: + +\DrawInsnTypeBPicture{BNE x3, x15, 2064}{00000000111100011001100011100011} + +imm[12:1] = $010000001000_2 = 1032_{10}$\\ +imm = $2064_{10}$\\ +funct3 = $001_2$\\ +rs1 = x3\\ +rs2 = x15 + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{BLT rs1, rs2, imm} +\index{Instruction!BLT} + +Branch if Less Than. + +\verb@pc@ $\leftarrow$ \verb@(rs1 < rs2) ? pc+sx(imm[12:1]<<1) : pc+4@ + +Encoding: + +\DrawInsnTypeBPicture{BLT x3, x15, 2064}{00000000111100011100100011100011} + +imm[12:1] = $010000001000_2 = 1032_{10}$\\ +imm = $2064_{10}$\\ +funct3 = $100_2$\\ +rs1 = x3\\ +rs2 = x15 + + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{BGE rs1, rs2, imm} +\index{Instruction!BGE} + +Branch if Greater or Equal. + +\verb@pc@ $\leftarrow$ \verb@(rs1 >= rs2) ? pc+sx(imm[12:1]<<1) : pc+4@ + +Encoding: + +\DrawInsnTypeBPicture{BGE x3, x15, 2064}{00000000111100011101100011100011} + +imm[12:1] = $010000001000_2 = 1032_{10}$\\ +imm = $2064_{10}$\\ +funct3 = $101_2$\\ +rs1 = x3\\ +rs2 = x15 + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{BLTU rs1, rs2, imm} +\index{Instruction!BLTU} + +Branch if Less Than Unsigned. + +\verb@pc@ $\leftarrow$ \verb@(rs1 < rs2) ? pc+sx(imm[12:1]<<1) : pc+4@ + +Encoding: + +\DrawInsnTypeBPicture{BLTU x3, x15, 2064}{00000000111100011110100011100011} + +imm[12:1] = $010000001000_2 = 1032_{10}$\\ +imm = $2064_{10}$\\ +funct3 = $110_2$\\ +rs1 = x3\\ +rs2 = x15 + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{BGEU rs1, rs2, imm} +\index{Instruction!BGEU} + +Branch if Greater or Equal Unsigned. + +\verb@pc@ $\leftarrow$ \verb@(rs1 >= rs2) ? pc+sx(imm[12:1]<<1) : pc+4@ + +Encoding: + +\DrawInsnTypeBPicture{BGEU x3, x15, 2064}{00000000111100011111100011100011} +\enote{use symbols in branch examples} + +imm[12:1] = $010000001000_2 = 1032_{10}$\\ +imm = $2064_{10}$\\ +funct3 = $111_2$\\ +rs1 = x3\\ +rs2 = x15 + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{LB rd, imm(rs1)} +\index{Instruction!LB} + +Load byte. + +\verb@rd@ $\leftarrow$ \verb@sx(m8(rs1+sx(imm)))@\\ +\verb@pc@ $\leftarrow$ \verb@pc+4@ + +Load an 8-bit value from memory at address \verb@rs1+imm@, then +sign--extend it to 32 bits before storing it in \verb@rd@ + + +Encoding: + +\DrawInsnTypeIPicture{LB x7, 4(x3)}{00000000010000011000001110000011} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{LH rd, imm(rs1)} +\index{Instruction!LH} + +Load halfword. + +\verb@rd@ $\leftarrow$ \verb@sx(m16(rs1+sx(imm)))@\\ +\verb@pc@ $\leftarrow$ \verb@pc+4@ + +Load a 16-bit value from memory at address \verb@rs1+imm@, then +sign--extend it to 32 bits before storing it in \verb@rd@ + + +Encoding: + +\DrawInsnTypeIPicture{LH x7, 4(x3)}{00000000010000011001001110000011} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{LW rd, imm(rs1)} +\index{Instruction!LW} + +Load word. + +\verb@rd@ $\leftarrow$ \verb@sx(m32(rs1+sx(imm)))@\\ +\verb@pc@ $\leftarrow$ \verb@pc+4@ + +Load a 32-bit value from memory at address \verb@rs1+imm@, then +store it in \verb@rd@ + +Encoding: + +\DrawInsnTypeIPicture{LW x7, 4(x3)}{00000000010000011010001110000011} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{LBU rd, imm(rs1)} +\index{Instruction!LBU} + +Load byte unsigned. + +\verb@rd@ $\leftarrow$ \verb@zx(m8(rs1+sx(imm)))@\\ +\verb@pc@ $\leftarrow$ \verb@pc+4@ + +Load an 8-bit value from memory at address \verb@rs1+imm@, then +zero--extend it to 32 bits before storing it in \verb@rd@ + +Encoding: + +\DrawInsnTypeIPicture{LBU x7, 4(x3)}{00000000010000011100001110000011} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{LHU rd, imm(rs1)} +\index{Instruction!LHU} + +Load halfword unsigned. + +\verb@rd@ $\leftarrow$ \verb@zx(m16(rs1+sx(imm)))@\\ +\verb@pc@ $\leftarrow$ \verb@pc+4@ + +Load an 16-bit value from memory at address \verb@rs1+imm@, then +zero--extend it to 32 bits before storing it in \verb@rd@ + +Encoding: + +\DrawInsnTypeIPicture{LHU x7, 4(x3)}{00000000010000011101001110000011} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{SB rs2, imm(rs1)} +\index{Instruction!SB} + +Store Byte. + +\verb@m8(rs1+sx(imm))@ $\leftarrow$ \verb@rs2[7:0]@\\ +\verb@pc@ $\leftarrow$ \verb@pc+4@ + +Store the 8-bit value in \verb@rs2[7:0]@ into memory at +address \verb@rs1+imm@. + +Encoding: + +\DrawInsnTypeSPicture{SB x3, 19(x15)}{00000000111100011000100110100011} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{SH rs2, imm(rs1)} +\index{Instruction!SH} + +Store Halfword. + +\verb@m16(rs1+sx(imm))@ $\leftarrow$ \verb@rs2[15:0]@\\ +\verb@pc@ $\leftarrow$ \verb@pc+4@ + +Store the 16-bit value in \verb@rs2[15:0]@ into memory at +address \verb@rs1+imm@. + + +Encoding: + +\DrawInsnTypeSPicture{SH x3, 19(x15)}{00000000111100011001100110100011} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{SW rs2, imm(rs1)} +\index{Instruction!SW} + +Store Word + +\verb@m16(rs1+sx(imm))@ $\leftarrow$ \verb@rs2[31:0]@\\ +\verb@pc@ $\leftarrow$ \verb@pc+4@ + +Store the 32-bit value in \verb@rs1@ into memory at address \verb@rs2+imm@. + +Encoding: + +\DrawInsnTypeSPicture{SW x3, 19(x15)}{00000000111100011010100110100011} + +Show pos \& neg imm examples. + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{ADDI rd, rs1, imm} +\index{Instruction!ADDI} + +Add Immediate + +\verb@rd@ $\leftarrow$ \verb@rs1+sx(imm)@\\ +\verb@pc@ $\leftarrow$ \verb@pc+4@ + +Encoding: + +\DrawInsnTypeIPicture{ADDI x1, x7, 4}{00000000010000111000000010010011} + +Before: + +x7 = 0x11111111 + +After: + +x1 = 0x11111115 + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{SLTI rd, rs1, imm} +\index{Instruction!SLTI} + +Set LessThan Immediate + +\verb@rd@ $\leftarrow$ \verb@(rs1 < sx(imm)) ? 1 : 0@\\ +\verb@pc@ $\leftarrow$ \verb@pc+4@ + +If the sign--extended immediate value is less than the value +in the \reg{rs1} register then the value 1 is stored in the +\reg{rd} register. Otherwise the value 0 is stored in the +\reg{rd} register. + +Encoding: + +\DrawInsnTypeIPicture{SLTI x1, x7, 4}{00000000010000111010000010010011} + +Before: + +x7 = 0x11111111 + +After: + +x1 = 0x00000000 + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{SLTIU rd, rs1, imm} +\index{Instruction!SLTIU} + +Set LessThan Immediate Unsigned + +\verb@rd@ $\leftarrow$ \verb@(rs1 < zx(imm)) ? 1 : 0@\\ +\verb@pc@ $\leftarrow$ \verb@pc+4@ + +If the zero--extended immediate value is less than the value +in the \reg{rs1} register then the value 1 is stored in the +\reg{rd} register. Otherwise the value 0 is stored in the +\reg{rd} register. Both the immediate and \reg{rs1} register +values are treated as unsigned numbers for the purposes of the +comparison. + +Encoding: + +\DrawInsnTypeIPicture{SLTIU x1, x7, 4}{00000000010000111011000010010011} + +Before: + +x7 = 0x81111111 + +After: + +x1 = 0x00000001 + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{XORI rd, rs1, imm} +\index{Instruction!XORI} + +Exclusive Or Immediate + +\verb@rd@ $\leftarrow$ \verb@rs1 ^ sx(imm)@\\ +\verb@pc@ $\leftarrow$ \verb@pc+4@ + +The logical XOR of the sign--extended immediate value and the value +in the \reg{rs1} register is stored in the \reg{rd} register. + +Encoding: + +\DrawInsnTypeIPicture{XORI x1, x7, 4}{00000000010000111100000010010011} + +Before: + +x7 = 0x81111111 + +After: + +x1 = 0x81111115 + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{ORI rd, rs1, imm} +\index{Instruction!ORI} + +Or Immediate + +\verb@rd@ $\leftarrow$ \verb@rs1 | sx(imm)@\\ +\verb@pc@ $\leftarrow$ \verb@pc+4@ + +The logical OR of the sign--extended immediate value and the value +in the \reg{rs1} register is stored in the \reg{rd} register. + +Encoding: + +\DrawInsnTypeIPicture{ORI x1, x7, 4}{00000000010000111110000010010011} + +Before: + +x7 = 0x81111111 + +After: + +x1 = 0x81111115 + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{ANDI rd, rs1, imm} +\index{Instruction!ANDI} + +And Immediate + +\verb@rd@ $\leftarrow$ \verb@rs1 & sx(imm)@\\ +\verb@pc@ $\leftarrow$ \verb@pc+4@ + +The logical AND of the sign--extended immediate value and the value +in the \reg{rs1} register is stored in the \reg{rd} register. + + +Encoding: + +\DrawInsnTypeIPicture{ANDI x1, x7, 4}{00000000010000111111000010010011} + +Before: + +x7 = 0x81111111 + +After: + +x1 = 0x81111115 + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{SLLI rd, rs1, shamt} +\index{Instruction!SLLI} + +Shift Left Logical Immediate + +\verb@rd@ $\leftarrow$ \verb@rs1 << shamt@\\ +\verb@pc@ $\leftarrow$ \verb@pc+4@ + + +SLLI is a logical left shift operation (zeros are shifted +into the lower bits). The value in rs1 shifted left shamt +number of bits and the result placed into rd.~\cite[p.~14]{rvismv1v22:2017} + +Encoding: + +\DrawInsnTypeRShiftPicture{SLLI x7, x3, 2}{00000000001000011001001110100011} + +x3 = 0x81111111 + +After: + +x7 = 0x04444444 + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{SRLI rd, rs1, shamt} +\index{Instruction!SRLI} + +Shift Right Logical Immediate + +\verb@rd@ $\leftarrow$ \verb@rs1 >> shamt@\\ +\verb@pc@ $\leftarrow$ \verb@pc+4@ + +SRLI is a logical right shift operation (zeros are shifted +into the higher bits). The value in rs1 shifted right shamt +number of bits and the result placed into rd.~\cite[p.~14]{rvismv1v22:2017} + + +Encoding: + +\DrawInsnTypeRShiftPicture{SRLI x7, x3, 2}{00000000001000011101001110010011} + +x3 = 0x81111111 + +After: + +x7 = 0x20444444 + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{SRAI rd, rs1, shamt} +\index{Instruction!SRAI} + +Shift Right Arithmetic Immediate + +\verb@rd@ $\leftarrow$ \verb@rs1 >> shamt@\\ +\verb@pc@ $\leftarrow$ \verb@pc+4@ + +SRAI is a logical right shift operation (zeros are shifted +into the higher bits). The value in rs1 shifted right shamt +number of bits and the result placed into rd.~\cite[p.~14]{rvismv1v22:2017} + +Encoding: + +\DrawInsnTypeRShiftPicture{SRAI x7, x3, 2}{01000000001000011101001110010011} + +x3 = 0x81111111 + +After: + +x7 = 0xe0444444 + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{ADD rd, rs1, rs2} +\index{Instruction!ADD} + +Add + +\verb@rd@ $\leftarrow$ \verb@rs1 + rs2@\\ +\verb@pc@ $\leftarrow$ \verb@pc+4@ + +ADD performs addition. Overflows are ignored and the low 32 bits of +the result are written to rd.~\cite[p.~15]{rvismv1v22:2017} + +Encoding: + +\DrawInsnTypeRPicture{ADD x7, x3, x31}{00000001111100011000001110110011} + +x3 = 0x81111111 +x31 = 0x22222222 + +After: + +x7 = 0xa3333333 + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{SUB rd, rs1, rs2} +\index{Instruction!SUB} + +Subtract + +\verb@rd@ $\leftarrow$ \verb@rs1 - rs2@\\ +\verb@pc@ $\leftarrow$ \verb@pc+4@ + +SUB performs subtraction. Underflows are ignored and the low 32 bits of +the result are written to rd.~\cite[p.~15]{rvismv1v22:2017} + +Encoding: + +\DrawInsnTypeRPicture{SUB x7, x3, x31}{01000001111100011000001110110011} + +x3 = 0x83333333 +x31 = 0x01111111 + +After: + +x7 = 0x82222222 + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{SLL rd, rs1, rs2} +\index{Instruction!SLL} + +Shift Left Logical + +\verb@rd@ $\leftarrow$ \verb@rs1 << rs2@\\ +\verb@pc@ $\leftarrow$ \verb@pc+4@ + +SLL performs a logical left shift on the value in register rs1 by +the shift amount held in the lower 5 bits of register rs2.~\cite[p.~15]{rvismv1v22:2017} + +Encoding: + +\DrawInsnTypeRPicture{SLL x7, x3, x31}{00000001111100011001001110110011} + +x3 = 0x83333333\\ +x31 = 0x00000002 + +After: + +x7 = 0x0ccccccc + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{SLT rd, rs1, rs2} +\index{Instruction!SLT} + +Set Less Than + +\verb@rd@ $\leftarrow$ \verb@(rs1 < rs2) ? 1 : 0@\\ +\verb@pc@ $\leftarrow$ \verb@pc+4@ + +SLT performs a signed compare, writing 1 to rd if rs1 < rs2, 0 +otherwise.~\cite[p.~15]{rvismv1v22:2017} + +Encoding: + +\DrawInsnTypeRPicture{SLT x7, x3, x31}{00000001111100011010001110110011} + +x3 = 0x83333333\\ +x31 = 0x00000002 + +After: + +x7 = 0x00000001 + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{SLTU rd, rs1, rs2} +\index{Instruction!SLTU} + +Set Less Than Unsigned + +\verb@rd@ $\leftarrow$ \verb@(rs1 < rs2) ? 1 : 0@\\ +\verb@pc@ $\leftarrow$ \verb@pc+4@ + +SLTU performs an unsigned compare, writing 1 to rd if rs1 < rs2, 0 otherwise. +Note, SLTU rd, x0, rs2 sets rd to 1 if rs2 is not equal to zero, otherwise +sets rd to zero (assembler pseudo-op SNEZ rd, rs).~\cite[p.~15]{rvismv1v22:2017} + +Encoding: + +\DrawInsnTypeRPicture{SLTU x7, x3, x31}{00000001111100011011001110110011} + +x3 = 0x83333333\\ +x31 = 0x00000002 + +After: + +x7 = 0x00000000 + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{XOR rd, rs1, rs2} +\index{Instruction!XOR} + +Exclusive Or + +\verb@rd@ $\leftarrow$ \verb@rs1 ^ rs2@\\ +\verb@pc@ $\leftarrow$ \verb@pc+4@ + +XOR performs a bit-wise exclusive or on rs1 and rs2. +The result is stored on rd. + +Encoding: + +\DrawInsnTypeRPicture{XOR x7, x3, x31}{00000001111100011100001110110011} + +x3 = 0x83333333\\ +x31 = 0x1888ffff + +After: + +x7 = 0x9bbbcccc + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{SRL rd, rs1, rs2} +\index{Instruction!SRL} + +Shift Right Logical + +\verb@rd@ $\leftarrow$ \verb@rs1 >> rs2@\\ +\verb@pc@ $\leftarrow$ \verb@pc+4@ + +SRL performs a logical right shift on the value in register rs1 by +the shift amount held in the lower 5 bits of +register rs2.~\cite[p.~15]{rvismv1v22:2017} + +Encoding: + +\DrawInsnTypeRPicture{SRL x7, x3, x31}{00000001111100011101001110110011} + +x3 = 0x83333333\\ +x31 = 0x00000010 + +After: + +x7 = 0x00008333 + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{SRA rd, rs1, rs2} +\index{Instruction!SRA} + +Shift Right Arithmetic + +\verb@rd@ $\leftarrow$ \verb@rs1 >> rs2@\\ +\verb@pc@ $\leftarrow$ \verb@pc+4@ + +SRA performs an arithmetic right shift (the original sign bit is copied +into the vacated upper bits) on the value in register rs1 by the shift +amount held in the lower 5 bits of +register rs2.~\cite[p.~14,~15]{rvismv1v22:2017} + +Encoding: + +\DrawInsnTypeRPicture{SLA x7, x3, x31}{01000001111100011101001110110011} + +x3 = 0x83333333\\ +x31 = 0x00000010 + +After: + +x7 = 0xffff8333 + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{OR rd, rs1, rs2} +\index{Instruction!OR} + +Or + +\verb@rd@ $\leftarrow$ \verb@rs1 | rs2@\\ +\verb@pc@ $\leftarrow$ \verb@pc+4@ + +OR is a logical operation that performs a bit-wise OR on +register rs1 and rs2 and then places the result +in rd.~\cite[p.~14]{rvismv1v22:2017} + +Encoding: + +\DrawInsnTypeRPicture{OR x7, x3, x31}{00000001111100011101001110110011} + +x3 = 0x83333333\\ +x31 = 0x00000440 + +After: + +x7 = 0x83333773 + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{AND rd, rs1, rs2} +\index{Instruction!AND} + +And + +\verb@rd@ $\leftarrow$ \verb@rs1 & rs2@\\ +\verb@pc@ $\leftarrow$ \verb@pc+4@ + +AND is a logical operation that performs a bit-wise AND on +register rs1 and rs2 and then places the result +in rd.~\cite[p.~14]{rvismv1v22:2017} + +Encoding: + +\DrawInsnTypeRPicture{AND x7, x3, x31}{00000001111100011110001110110011} + +x3 = 0x83333333\\ +x31 = 0x00000fe2 + +After: + +x7 = 0x00000322 + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{FENCE predecessor, successor} +\index{Instruction!FENCE} + +The FENCE instruction is used to order device I/O and memory accesses as +viewed by other RISC-V harts and external devices or co-processors. Any +combination of device input (I), device output (O), memory reads (R), +and memory writes (W) may be ordered with respect to any combination +of the same. Informally, no other RISC-V hart or external device can +observe any operation in the successor set following a FENCE before any +operation in the predecessor set preceding the FENCE. The execution +environment will define what I/O operations are possible, and in particular, +which load and store instructions might be treated and ordered as device +input and device output operations respectively rather than memory reads +and writes. For example, memory-mapped I/O devices will typically be +accessed with uncached loads and stores that are ordered using the I and O + bits rather than the R and W bits. Instruction-set extensions might +also describe new coprocessor I/O instructions that will also be ordered +using the I and O bits in a FENCE.~\cite[p.~21]{rvismv1v22:2017} + +Operation: + +\verb@pc@ $\leftarrow$ \verb@pc+4@ + +Encoding: + +%\insnTypeF{FENCE iorw, iorw} +{0 0 0 1 1 1 1} % op +{0 0 0} % funct3 +{1 1 1 1} % predecessor iorw +{1 1 1 1} % successor iorw + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{FENCE.I} +\index{Instruction!FENCE.I} + +The FENCE.I instruction is used to synchronize the instruction and +data streams. RISC-V does not guarantee that stores to instruction +memory will be made visible to instruction fetches on the same +RISC-V hart until a FENCE.I instruction is executed. A FENCE.I +instruction only ensures that a subsequent instruction fetch on +a RISC-V hart will see any previous data stores already visible to +the same RISC-V hart. FENCE.I does not ensure that other RISC-V harts' +instruction fetches will observe the local hart's stores in a +multiprocessor system. To make a store to instruction memory +visible to all RISC-V harts, the writing hart has to execute a +data FENCE before requesting that all remote RISC-V harts execute +a FENCE.I.~\cite[p.~21]{rvismv1v22:2017} + +Operation: + +\verb@pc@ $\leftarrow$ \verb@pc+4@ + +Encoding: + +%\insnTypeF{FENCE.I} +{0 0 0 1 1 1 1} % op +{0 0 1} % funct3 +{0 0 0 0} % predecessor iorw +{0 0 0 0} % successor iorw + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{ECALL} +\index{Instruction!ECALL} + +The ECALL instruction is used to make a request to the supporting +execution environment, which is usually an operating system. The ABI +for the system will define how parameters for the environment +request are passed, but usually these will be in defined locations +in the integer register file.~\cite[p.~24]{rvismv1v22:2017} + +%\insnTypeI{ECALL} +{1 1 1 0 0 1 1} +{0 0 0 0 0} +{0 0 0} +{0 0 0 0 0} +{0 0 0 0 0 0 0 0 0 0 0 0} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{EBREAK} +\index{Instruction!EBREAK} + +The EBREAK instruction is used by debuggers to cause control to be +transferred back to a debugging environment.~\cite[p.~24]{rvismv1v22:2017} + +%\insnTypeI{ECALL} +{1 1 1 0 0 1 1} +{0 0 0 0 0} +{0 0 0} +{0 0 0 0 0} +{0 0 0 0 0 0 0 0 0 0 0 1} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{CSRRW rd, csr, rs1} +\index{Instruction!CSRRW} + +The CSRRW (Atomic Read/Write CSR) instruction atomically swaps values in +the CSRs and integer registers. CSRRW reads the old value of the CSR, +zero-extends the value to XLEN bits, then writes it to integer register rd. +The initial value in rs1 is written to the CSR. If rd=x0, then the +instruction shall not read the CSR and shall not cause any of the +side-effects that might occur on a CSR read.~\cite[p.~22]{rvismv1v22:2017} + +%\insnTypeCSRR{CSRRW x3, 2, x15} +{1 1 1 0 0 1 1} % op +{0 0 0 1 1} % rd +{0 0 1} % funct3 +{0 1 1 1 1} % rs1 +{0 0 0 0 0 0 0 0 0 0 1 0} % csr + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{CSRRS rd, csr, rs1} +\index{Instruction!CSRRS} + +The CSRRS (Atomic Read and Set Bits in CSR) instruction reads the value +of the CSR, zero-extends the value to XLEN bits, and writes it to integer +register rd. The initial value in integer register rs1 is treated as a bit +mask that specifies bit positions to be set in the CSR. Any bit that +is high in rs1 will cause the corresponding bit to be set in the CSR, +if that CSR bit is writable. Other bits in the CSR are unaffected (though +CSRs might have side effects when written).~\cite[p.~22]{rvismv1v22:2017} + +If rs1=x0, then the instruction will not write +to the CSR at all, and so shall not cause any of the side effects that +might otherwise occur on a CSR write, such as raising illegal instruction +exceptions on accesses to read-only CSRs. Note that if rs1 specifies a +register holding a zero value other than x0, the instruction will still +attempt to write the unmodified value back to the CSR and will cause any +attendant side effects.~\cite[p.~22]{rvismv1v22:2017} + + +%\insnTypeCSRR{CSRRS x3, 2, x15} +{1 1 1 0 0 1 1} % op +{0 0 0 1 1} % rd +{0 1 0} % funct3 +{0 1 1 1 1} % rs1 +{0 0 0 0 0 0 0 0 0 0 1 0} % csr + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{CSRRC rd, csr, rs1} +\index{Instruction!CSRRC} + +The CSRRC (Atomic Read and Clear Bits in CSR) instruction reads the value +of the CSR, zero-extends the value to XLEN bits, and writes it to integer +register rd. The initial value in integer register rs1 is treated as a +bit mask that specifies bit positions to be cleared in the CSR. Any bit +that is high in rs1 will cause the corresponding bit to be cleared in +the CSR, if that CSR bit is writable. Other bits in the CSR are +unaffected.~\cite[p.~22]{rvismv1v22:2017} + +If rs1=x0, then the instruction will not write +to the CSR at all, and so shall not cause any of the side effects that +might otherwise occur on a CSR write, such as raising illegal instruction +exceptions on accesses to read-only CSRs. Note that if rs1 specifies a +register holding a zero value other than x0, the instruction will still +attempt to write the unmodified value back to the CSR and will cause any +attendant side effects.~\cite[p.~22]{rvismv1v22:2017} + +%\insnTypeCSRR{CSRRC x3, 2, x15} +{1 1 1 0 0 1 1} % op +{0 0 0 1 1} % rd +{0 1 1} % funct3 +{0 1 1 1 1} % rs1 +{0 0 0 0 0 0 0 0 0 0 1 0} % csr + + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{CSRRWI rd, csr, imm} +\index{Instruction!CSRRWI} + +This instruction is the same as CSRRW except a 5-bit unsigned (zero-extended) +immediate value is used rather than the value from a register. + +%\insnTypeCSRR{CSRRWI x3, 2, 7} +{1 1 1 0 0 1 1} % op +{0 0 0 1 1} % rd +{1 0 1} % funct3 +{0 0 1 1 1} % imm +{0 0 0 0 0 0 0 0 0 0 1 0} % csr + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{CSRRSI rd, csr, rs1} +\index{Instruction!CSRRSI} + +This instruction is the same as CSRRS except a 5-bit unsigned (zero-extended) +immediate value is used rather than the value from a register. + +If the uimm[4:0] field is zero, then this instruction will not +write to the CSR, and shall not cause any of the side effects that +might otherwise occur on a CSR write. For CSRRWI, if rd=x0, then +the instruction shall not read the CSR and shall not cause any +of the side-effects that might occur on a CSR +read.~\cite[p.~22]{rvismv1v22:2017} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{CSRRCI rd, csr, rs1} +\index{Instruction!CSRRCI} + +This instruction is the same as CSRRC except a 5-bit unsigned (zero-extended) +immediate value is used rather than the value from a register. + +If the uimm[4:0] field is zero, then this instruction will not +write to the CSR, and shall not cause any of the side effects that +might otherwise occur on a CSR write. For CSRRWI, if rd=x0, then +the instruction shall not read the CSR and shall not cause any +of the side-effects that might occur on a CSR +read.~\cite[p.~22]{rvismv1v22:2017} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\section{RV32M Standard Extension} +\index{RV32M} + +32-bit integer multiply and divide instructions. + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\section{RV32A Standard Extension} +\index{RV32A} + +32-bit atomic operations. + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\section{RV32F Standard Extension} +\index{RV32F} + +32-bit IEEE floating point instructions. + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\section{RV32D Standard Extension} +\index{RV32D} + +64-bit IEEE floating point instructions. diff --git a/book/toolchain/chapter.tex b/book/toolchain/chapter.tex new file mode 100644 index 0000000..e2945ec --- /dev/null +++ b/book/toolchain/chapter.tex @@ -0,0 +1,93 @@ +\chapter{The RISC-V GNU Toolchain} + +This chapter discusses the GNU toolchain elements used to +experiment with the material in this book. + +The\enote{It would be good to find some Mac and Windows users to write +and test proper variations on this section to address those systems. +Pull requests, welcome!} +instructions and examples here were all implemented on Ubuntu 16.04 LTS. + +Install custom code in a location that will not cause interference with +other applications and allow for easy cleanup. These instructions +install the toolchain in \verb@/usr/local/riscv@. At any time +you can remove the lot and start over by executing the following +command: + +\begin{verbatim} +rm -rf /usr/local/riscv/* +\end{verbatim} + + +Tested on Ubuntu 16.04 LTS. +18.04 was just released\ldots\ update accordingly. + +These are the only commands that you should perform as root when installing +the toolchain: + +\begin{verbatim} +sudo apt-get install autoconf automake autotools-dev curl libmpc-dev \ + libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf \ + libtool patchutils bc zlib1g-dev libexpat-dev +sudo mkdir -p /usr/local/riscv/ +chmod 777 /usr/local/riscv/ +\end{verbatim} + +All other commands should be executed as a regular user. This will eliminate the +possibility of clobbering system files that should not be touched when tinkering with +the toolchain applicaitons. + +To download, compile and ``install'' the toolchain: + +\begin{verbatim} +# riscv toolchain: +# +# https://riscv.org/software-tools/risc-v-gnu-compiler-toolchain/ + +git clone --recursive https://github.com/riscv/riscv-gnu-toolchain +cd riscv-gnu-toolchain +./configure --prefix=/usr/local/riscv --with-arch=rv32im --with-abi=ilp32 +make +make install +\end{verbatim} + +Need to discuss augmenting the PATH environment variable. + +Discuss the choice of ilp32 as well as what the other variations would do. + +Discuss rv32im and note that the details are found in \autoref{chapter:RV32}. + +Disciuss installing and using one of the RISC-V simulators +here. + +Describe the pre-processor, compiler, assemler and linker. + +Source, object, and binary files + +Assembly syntax (label: mnemonic op1, op2, op3 \# comment). + +text, data, bss, stack + +Labels and scope. + +Forward \& backward references to throw--away labels. + +The entry address of an application. + +.s file contain assembler code. +.S (or .sx) files contain assembler code that must be preprocessed.~\cite[p.~29]{gcc:2017} + +Pre-processing conditional assembly using \#if. + +Building with \verb@-mabi=ilp32 -march=rv32i -mno-fdiv -mno-div@ to match +the config options on the toolchain. + +Linker scripts. + +Makefiles + +objdump + +nm + +hexdump -C