diff --git a/README.md b/README.md index 8e12e8d..54047ba 100644 --- a/README.md +++ b/README.md @@ -17,7 +17,7 @@ be able to tinker with it on most any platform. The following worked for me on Ubuntu 16.04 LTS: - sudo apt install wget gksu perl-tk + sudo apt install wget perl-tk wget http://mirror.ctan.org/systems/texlive/tlnet/install-tl-unx.tar.gz tar -xzf install-tl-unx.tar.gz cd install-tl-20180303 @@ -28,9 +28,9 @@ coffee, do some laundry...] Put the following into .bashrc: - export PATH=/usr/local/texlive/2017/bin/x86_64-linux:$PATH - export INFOPATH=$INFOPATH:/usr/local/texlive/2017/texmf-dist/doc/info - export MANPATH=$MANPATH:/usr/local/texlive/2017/texmf-dist/doc/man + export PATH=/usr/local/texlive/2018/bin/x86_64-linux:$PATH + export INFOPATH=$INFOPATH:/usr/local/texlive/2018/texmf-dist/doc/info + export MANPATH=$MANPATH:/usr/local/texlive/2018/texmf-dist/doc/man Then clone and build this repo: diff --git a/book/binary/chapter.tex b/book/binary/chapter.tex index a709ab5..82cdc3b 100644 --- a/book/binary/chapter.tex +++ b/book/binary/chapter.tex @@ -11,6 +11,17 @@ RISC-V assembly language uses binary to represent all values, be they boolean or numeric. It is the context within which they are used that determines whether they are boolean or numeric. +\enote{Add some diagrams here showing bits, bytes and the MSB, +LSB,\ldots\ perhaps relocated from the RV32I chapter?} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\section{Boolean Functions} + +Boolean functions apply on a per-bit basis. +When applied to multi-bit values, each bit position is operated upon +independently of the other bits. + RISC-V assembly language uses zero to represent {\em false} and one to represent {\em true}. In general, however, it is useful to relax this and define zero {\bf and only zero} to be {\em false} and anything @@ -19,27 +30,11 @@ that is not {\em false} is therefore {\em true}.% many other languages as well as the common assembly language idioms discussed in this text.} -\enote{Add some diagrams here showing bits, bytes and the MSB, -LSB,\ldots\ perhaps relocated from the RV32I chapter?}% The reason for this relaxation is because, while a single binary digit (\gls{bit}) can represent the two values zero and one, the vast majority of the time data is processed by the CPU in groups of bits. These -groups have names like \gls{byte}, \gls{halfword} and \gls{fullword}. - - - -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\section{Boolean Functions} - -\enote{Probably should add basic truth table diagrams.}% -Boolean functions apply on a per-bit basis. -%in that they do not impact neighboring bits. -%by generating things like a carry or a borrow. -When applied to multi-bit values, each bit position is operated upon -independently of the other bits. - - +groups have names like \gls{byte} (8 bits), \gls{halfword} (16 bits) +and \gls{fullword} (32 bits). %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% @@ -54,9 +49,35 @@ If the input is 1 then the output is 0. If the input is 0 then the output is 1. In other words, the output value is {\em not} that of the input value. -This text will use the operator used in the C language when discussing +Expressing the {\em not} function in the form a a truth table: + +\begin{center} +\begin{tabular}{c|c} +A & $\overline{\mbox{A}}$\\ +\hline +0 & 1 \\ +1 & 0 \\ +\end{tabular} +\end{center} + +A truth table is drawn by indicating all of the possible input values on +the left of the vertical bar with each row displaying the output values +that correspond to the input for that row. The column headings are used +to define the illustrated operation expressed using a mathematical +notation. The {\em not} operation is indicated by the presense of +an {\em overline}. + +In computer programming languages, things like an overline can not be +efficiently expressed using a standard keyboard. Therefore it is common +to use a notation such as that used by the C language when discussing the {\em NOT} operator in symbolic form. Specifically the tilde: `\verb@~@'. +It is also uncommon to for programming languages to express boolean operations +on single-bit input(s). A more generalized operation is used that applies +to a set of bits all at once. For example, performing a {\em not} operation +of eight bits at once can be illustrated as: + + \begin{verbatim} ~ 1 1 1 1 0 1 0 1 <== A ----------------- @@ -73,12 +94,30 @@ The boolean {\em and} function has two or more inputs and the output is a single bit. The output is 1 if and only if all of the input values are 1. Otherwise it is 0. +This function works like it does in spoken language. For example +if A is 1 {\em AND} B is 1 then the output is 1 (true). +Otherwise the output is 0 (false). + +In mathamatical notion, the {\em and} operator is expressed the same way +as is {\em multiplication}. That is by a raised dot between, or by +juxtaposition of, two variable names. It is also worth noting that, +in base-2, the {\em and} operation actually {\em is} multiplication! + +\begin{center} +\begin{tabular}{cc|c} +A & B & AB \\ +\hline +0 & 0 & 0 \\ +0 & 1 & 0 \\ +1 & 0 & 0 \\ +1 & 1 & 1 \\ +\end{tabular} +\end{center} + This text will use the operator used in the C language when discussing the {\em AND} operator in symbolic form. Specifically the ampersand: `\verb@&@'. -This function works like it does in spoken language. For example -if A is 1 {\em AND} B is 1 then the output is 1 (true). -Otherwise the output is 0 (false). For example: +An eight-bit example: \begin{verbatim} 1 1 1 1 0 1 0 1 <== A @@ -96,12 +135,28 @@ In a line of code the above might read like this: \verb@output = A & B@ The boolean {\em or} function has two or more inputs and the output is a single bit. The output is 1 if at least one of the input values are 1. +This function works like it does in spoken language. For example +if A is 1 {\em OR} B is 1 then the output is 1 (true). +Otherwise the output is 0 (false). + +In mathamatical notion, the {\em or} operator is expressed using the plus +($+$). + +\begin{center} +\begin{tabular}{cc|c} +A & B & A$+$B \\ +\hline +0 & 0 & 0 \\ +0 & 1 & 1 \\ +1 & 0 & 1 \\ +1 & 1 & 1 \\ +\end{tabular} +\end{center} + This text will use the operator used in the C language when discussing the {\em OR} operator in symbolic form. Specifically the pipe: `\verb@|@'. -This function works like it does in spoken language. For example -if A is 1 {\em OR} B is 1 then the output is 1 (true). -Otherwise the output is 0 (false). For example: +An eight-bit example: \begin{verbatim} 1 1 1 1 0 1 0 1 <== A @@ -120,14 +175,29 @@ The boolean {\em exclusive or} function has two or more inputs and the output is a single bit. The output is 1 if only an odd number of inputs are 1. Otherwise the output will be 0. -This text will use the operator used in the C language when discussing -the {\em XOR} operator in symbolic form. Specifically the carrot: `\verb@^@'. - Note that when {\em XOR} is used with two inputs, the output is set to 1 (true) when the inputs have different values and 0 (false) when the inputs both have the same value. -For example: +In mathamatical notion, the {\em xor} operator is expressed using the plus +in a circle ($\oplus$). + +\begin{center} +\begin{tabular}{cc|c} +A & B & A$\oplus{}$B \\ +\hline +0 & 0 & 0 \\ +0 & 1 & 1 \\ +1 & 0 & 1 \\ +1 & 1 & 0 \\ +\end{tabular} +\end{center} + +This text will use the operator used in the C language when discussing +the {\em XOR} operator in symbolic form. Specifically the carrot: `\verb@^@'. + + +An eight-bit example: \begin{verbatim} 1 1 1 1 0 1 0 1 <== A @@ -200,9 +270,9 @@ $10^2$ & $10^1$ & $10^0$ & $2^7$ & $2^6$ & $2^5$ & $2^4$ & $2^3$ & $2^2$ & $2^1$ One way to look at this table is on a per-row basis where each place value is represented by the base raised to the power of the place value -position (shown in the column headings.) This is useful when -converting arbitrary values between bases. For example to interpret -the decimal value on the fourth row: +position (shown in the column headings.) +%This is useful when converting arbitrary numeric values between bases. +For example to interpret the decimal value on the fourth row: \begin{equation} 0 \times 10^2 + 0 \times 10^1 + 3 \times 10^0 = 3_{10} @@ -220,6 +290,15 @@ Interpreting the hexadecimal value on the fourth row by converting it to decimal 0 \times 16^1 + 3 \times 16^0 = 3_{10} \end{equation} +\index{Most significant bit}\index{MSB|see {Most significant bit}}% +\index{Least significant bit}\index{LSB|see {Least significant bit}}% +We refer to the place values with the largest exponenet (the one furthest to the +left for any given base) as the {\em most significant} digit and the place value +with the lowest exponenet as the {\em least significant} digit. For binary +numbers these are the \acrfull{msb} and \acrfull{lsb} respectively.% +\footnote{Changing the value of the MSB will have a more {\em significant} +impact on the numeric value than changing the value of the LSB.} + Another way to look at this table is on a per-column basis. When tasked with drawing such a table by hand, it might be useful @@ -242,8 +321,8 @@ for readability. The relationship between binary and hex values is also worth taking note. Because $2^4 = 16$, there is a clean and simple grouping -of 4 \gls{bit}s to 1 \gls{hit}. There is no such relationship -between binary and decimal. +of 4 \gls{bit}s to 1 \gls{hit} (aka \gls{nybble}). +There is no such relationship between binary and decimal. Writing and reading numbers in binary that are longer than 8 bits is cumbersome and prone to error. The simple conversion between @@ -283,8 +362,9 @@ To convert from binary to decimal, put the decimal value of the place values {\ldots8 4 2 1} over the binary digits like this: \begin{verbatim} - 128 64 32 16 8 4 2 1 - 0 0 0 1 1 0 1 1 +Base-2 place values: 128 64 32 16 8 4 2 1 +Binary: 0 0 0 1 1 0 1 1 +Decimal: 16 +8 +2 +1 = 27 \end{verbatim} Now sum the place-values that are expressed in decimal for each @@ -303,9 +383,9 @@ extend the binary to the left with zeros to make it so. Grouping the bits into sets of four and summing: \begin{verbatim} -Place: 8 4 2 1 8 4 2 1 8 4 2 1 8 4 2 1 -Binary: 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 0 -Decimal: 4+2 =6 8+4+ 1=13 8+ 2 =10 8+4+2 =14 +Base-2 place values: 8 4 2 1 8 4 2 1 8 4 2 1 8 4 2 1 +Binary: 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 0 +Decimal: 4+2 =6 8+4+ 1=13 8+ 2 =10 8+4+2 =14 \end{verbatim} After the summing, convert each decimal value to hex. The decimal @@ -339,10 +419,9 @@ method discussed in \autoref{section:bindec}. For example: \begin{verbatim} -Hex: 4 C -Binary: 0 1 0 0 1 1 0 0 -Decimal: 128 64 32 16 8 4 2 1 -Sum: 64+ 8+4 = 76 +Hex: 7 C +Decimal Sum: 4+2+1=7 8+4 =12 +Binary: 0 1 1 1 1 1 0 0 \end{verbatim} @@ -356,8 +435,9 @@ of the place values that would yield a non-negative result. For example, to convert $1234_{10}$ to binary: + \begin{verbatim} -Place values: 2048-1024-512-256-128-64-32-16-8-4-2-1 +Base-2 place values: 2048-1024-512-256-128-64-32-16-8-4-2-1 0 2048 (too big) 1 1234 - 1024 = 210 @@ -429,20 +509,46 @@ negate the place value of the \acrshort{msb}. For example, the number one is represented the same as discussed before: \begin{verbatim} - -128 64 32 16 8 4 2 1 - 0 0 0 0 0 0 0 1 +Base-2 place values: -128 64 32 16 8 4 2 1 +Binary: 0 0 0 0 0 0 0 1 \end{verbatim} The \acrshort{msb} of any negative number in this format will always be 1. For example the value $-1_{10}$ is: \begin{verbatim} - -128 64 32 16 8 4 2 1 - 1 1 1 1 1 1 1 1 +Base-2 place values: -128 64 32 16 8 4 2 1 +Binary: 1 1 1 1 1 1 1 1 \end{verbatim} \ldots because: $-128+64+32+16+8+4+2+1=-1$. + +Calculating $4+5 = 9$ + +\begin{verbatim} + 1 <== carries + 000100 <== 4 + +000101 <== 5 + ------ + 001001 <== 9 +\end{verbatim} + +Calculating $-4+ -5 = -9$ + +\begin{verbatim} + 1 11 <== carries + 111100 <== -4 + +111011 <== -5 + --------- + 1 110111 <== -9 (with a truncation) + + -32 16 8 4 2 1 + 1 1 0 1 1 1 + -32 + 16 + 4 + 2 + 1 = -9 +\end{verbatim} + + This format has the virtue of allowing the same addition logic discussed above to be used to calculate $-1+1=0$. @@ -452,11 +558,11 @@ discussed above to be used to calculate $-1+1=0$. 1 1 1 1 1 1 1 1 <== addend (-1) + 0 0 0 0 0 0 0 1 <== addend (1) ---------------------- - 1 0 0 0 0 0 0 0 0 <== sum (0 with an overflow) + 1 0 0 0 0 0 0 0 0 <== sum (0 with a truncation) \end{verbatim} -In order for this to work, the \gls{overflow} carry out of the -sum of the MSBs is ignored. +In order for this to work, the carry out of the sum of the MSBs is +ignored. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsubsection{Converting between Positive and Negative} @@ -623,10 +729,78 @@ the results of ADD and ADDW on the operands. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{Sign and Zero Extension} -\enote{Refactor the sx() and zx() discussion in the RV32I chapter -and locate the details here.}% -Seems like a good place to discuss extension. +\index{sign extension} +\label{SignExtension} +Due to the nature of the two's complement encoding scheme, the following +numbers all represent the same value: +\begin{verbatim} + 1111 <== -1 + 11111111 <== -1 + 11111111111111111111 <== -1 + 1111111111111111111111111111 <== -1 +\end{verbatim} +As do these: +\begin{verbatim} + 01100 <== 12 + 0000001100 <== 12 + 00000000000000000000000000000001100 <== 12 +\end{verbatim} +The phenomenon illustrated here is called {\em sign extension}. That is +any signed number can have any quantity of additional MSBs added to it, +provided that they repeat the value of the sign bit. + +\autoref{Figure:SignExtendNegative} illustrates extending the negative sign +bit of {\em val} to the left by replicating it. +When {\em val} is negative, its \acrshort{msb} (bit 19 in this example) will +be set to 1. Extending this value to the left will set all the new bits +to the left of it to 1 as well. + +\begin{figure}[ht] +\centering +\DrawBitBoxSignExtendedPicture{32}{10100000000000000010} +\captionof{figure}{Sign-extending a negative integer from 20 bits to 32 bits.} +\label{Figure:SignExtendNegative} +\end{figure} + +\autoref{Figure:SignExtendPositive} illustrates extending the positive sign +bit of {\em val} to the left by replicating it. +When {\em val} is positive, its \acrshort{msb} will be set to 0. Extending this +value to the left will set all the new bits to the left of it to 0 as well. + +\begin{figure}[ht] +\centering +\DrawBitBoxSignExtendedPicture{32}{01000000000000000010} +\captionof{figure}{Sign-extending a positive integer from 20 bits to 32 bits.} +\label{Figure:SignExtendPositive} +\end{figure} + + +\label{ZeroExtension} +In a similar vein, any {\em unsigned} number also may have any quantity of +additional MSBs added to it provided that htey are all zero. For example, +the following all represent the same value: +\begin{verbatim} + 1111 <== 15 + 01111 <== 15 + 00000000000000000000000001111 <== 15 +\end{verbatim} + +The observation here is that any {\em unsigned} number may be +{\em zero extended} to any size. + +\autoref{Figure:ZeroExtend} illustrates zero-extending a 20-bit {\em val} to the +left to form a 32-bit fullword. + +\begin{figure}[ht] +\centering +\DrawBitBoxZeroExtendedPicture{32}{10000000000000000010} +\captionof{figure}{Zero-extending an unsigned integer from 20 bits to 32 bits.} +\label{Figure:ZeroExtend} +\end{figure} + +%Sign- and zero-extending binary numbers are common operations used to +%fit a byte or halfword into a fullword. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% @@ -694,28 +868,59 @@ value and TRUE if it is a conditional. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Alignment} -Draw a diagram showing the overlapping data types when they are all aligned. +\enote{Include the obligatory diagram showing the overlapping data types +when they are all aligned.}% +With respect to memory and storage, {\em \gls{alignment}} refers to the +{\em location} of a data element when the address that it is stored is +a precise multiple of a power-of-2. + +The primary alignments of concern are typically 2 (a halfword), +4 (a fullword), 8 (a double word) and 16 (a quad-word) bytes. + +For example, any data element that is aligned to 2-byte boundary +must have an (hex) address that ends in any of: 0, 2, 4, 6, 8, A, +C or E. +Any 4-byte aligned element must be located at an address ending +in 0, 4, 8 or C. An 8-byte aligned element at an address ending +with 0 or 8, and 16-byte aligned elements must be located at +addresses ending in zero. + +Such alignments are important when exchanging data between the CPU +and memory because the hardware implementations are optimized to +transfer aligned data. Therefore, aligning data used by any program +will reap the benefit of running faster. + +An element of data is considered to be {\em aligned to its natural size} +when its address is an exact multiple of the number of bytes used to +represent the data. Note that the ISA we are concerned with {\em only} +operates on elements that have sizes that are powers of two. + +For example, a 32-bit integer consumes one full word. If the four bytes +are stored in main memory at an address than is a multiple of 4 then +the integer is considered to naturally aligned. + +The same would apply to 16-bit, 64-bit, 128-bit and other such values +as they fit into 2, 8 and 16 byte elements respectively. + +Some CPUs can deliver four (or more) bytes at the same time while others +might only be capable of delivering one or two bytes at a time. Such +differences in hardware typically impact the cost and performance of a +system.% +\footnote{The design and implementation +choices that determine how any given system operates are part of what is +called a system's {\em organization} and is beyond the scope of this text. +See~\cite{codriscv:2017} for more information on computer organization.} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Instruction Alignment} -\enote{Rewrite this section for data rather than instructions and then -note here that instructions must be naturally aligned. For RV32 that -is on a 4-byte boundary}% +The RISC-V ISA requires that all instructions be aligned to their +natural boundaries. + Every possible instruction that an RV32I CPU can execute contains -exactly 32 bits. Therefore each one must be stored in four bytes -of the main memory. - -To simplify the hardware, each instruction must be placed into four -adjacent bytes whose numeric address sequence begins with a multiple -four. For example, an instruction might be located in bytes -4, 5, 6 and 7 (but not in 5, 6, 7 and 8 nor in 9, 3, 1, and 0\ldots). - -This sort of addressing requirement is common and is referred to as -\gls{alignment}. An aligned instruction begins at a memory address -that is a multiple of four. An {\em unaligned} instruction would -be one beginning at any other address and is {\em illegal}. +exactly 32 bits. Therefore they are always stored on a full word +boundary. Any {\em unaligned} instruction would is {\em illegal}. An attempt to fetch an instruction from an unaligned address will result in an error referred to as an alignment {\em \gls{exception}}. @@ -724,15 +929,3 @@ current instruction and start executing a different set of instructions that are prepared to handle the problem. Often an exception is handled by completely stopping the program in a way that is commonly referred to as a system or application {\em crash}. - -Given a properly aligned instruction address, the CPU can request -that the main memory locate and deliver the values of the four bytes -in the address sequence to the CPU using what is called a memory -read operation. Some systems can deliver four (or more) bytes at the -same time while others might only be capable of delivering one or -two bytes at a time. These differences in hardware typically impact the -cost and performance of a system.\footnote{The design and implementation -choices that determine how any given system operates are part of what is -called a system's {\em organization} and is beyond the scope of this text. -See~\cite{codriscv:2017} for more information on computer organization.} - diff --git a/book/book.tex b/book/book.tex index d6736f8..a3eecbe 100644 --- a/book/book.tex +++ b/book/book.tex @@ -2,6 +2,7 @@ %\documentclass[letterpaper]{book} \documentclass[oneside,letterpaper]{book} + \input{preamble} \input{colors} \input{insnformats} @@ -22,10 +23,11 @@ \makenoidxglossaries \include{glossary} +%\includeonly{refcard/chapter} + \begin{document} \include{indexrefs} % The see-references for the index - % Why does this (apparently) have to go here???? \newlength{\fullwidth} \setlength{\fullwidth}{\the\textwidth} @@ -61,7 +63,6 @@ \include{intro/chapter} \include{binary/chapter} \include{elements/chapter} -\include{toolchain/chapter} \include{programs/chapter} \include{rv32/chapter} @@ -69,7 +70,9 @@ % These 'chapters' are lettered rather than numbered \appendix +\include{insnsummary/chapter} \include{install/chapter} +\include{toolchain/chapter} \include{float/chapter} \include{ascii/chapter} \include{license/chapter} @@ -78,25 +81,22 @@ \backmatter % putting a chapter here causes it to be unnumbered - -%\clearpage \bibliography{bibliography} \addcontentsline{toc}{chapter}{Bibliography} \nocite{*} % force all bib items to file appear even if not cited %\bibliographystyle{alpha} \bibliographystyle{ieeetr} -%\clearpage %\phantomsection \glsaddall \printnoidxglossaries %\printglossary -%\clearpage \phantomsection \addcontentsline{toc}{chapter}{\indexname} \printindex +\include{refcard/chapter} \end{document} diff --git a/book/float/chapter.tex b/book/float/chapter.tex index f0c277b..4844a23 100644 --- a/book/float/chapter.tex +++ b/book/float/chapter.tex @@ -1,5 +1,5 @@ \chapter{Floating Point Numbers} -\label{chapter:NumberSystems} +\label{chapter:floatingpoint} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% diff --git a/book/glossary.tex b/book/glossary.tex index 9fd0445..bd43ce3 100644 --- a/book/glossary.tex +++ b/book/glossary.tex @@ -2,7 +2,7 @@ { name=LaTeX, description={Is a mark up language specially suited - for scientific documents} + for scientific documents} } \newglossaryentry{binary} @@ -10,13 +10,13 @@ name=binary, description={Something that has two parts or states. In computing these two states are represented by the numbers one and zero or - by the conditions true and false and can be stored in one bit} + by the conditions true and false and can be stored in one \gls{bit}} } \newglossaryentry{hexadecimal} { name=hexadecimal, - description={A base-16 numbering system whose digits are - 0123456789abcdef. The hex digits (hits) are not case-sensitive} + description={A base-16 numbering system whose digits are 0123456789abcdef. + The hex digits (\gls{hit}s) are not case-sensitive} } \newglossaryentry{bit} { @@ -26,59 +26,65 @@ \newglossaryentry{hit} { name={hit}, - description={One hex digit} + description={One \gls{hexadecimal} digit} +} +\newglossaryentry{nybble} +{ + name={nybble}, + description={Half of a {\em \gls{byte}} is a {\em nybble} + (sometimes spelled nibble.) Another word for {\em \gls{hit}}} } \newglossaryentry{byte} { name=byte, - description={A binary value represented by 8 bits} + description={A \gls{binary} value represented by 8 \gls{bit}s} } \newglossaryentry{halfword} { name={halfword}, - description={A binary value represented by 16 bits} + description={A \gls{binary} value represented by 16 \gls{bit}s} } \newglossaryentry{fullword} { name={fullword}, - description={A binary value represented by 32 bits} + description={A \gls{binary} value represented by 32 \gls{bit}s} } \newglossaryentry{doubleword} { name={doubleword}, - description={A binary value represented by 64 bits} + description={A \gls{binary} value represented by 64 \gls{bit}s} } \newglossaryentry{quadword} { name={quadword}, - description={A binary value represented by 128 bits} + description={A \gls{binary} value represented by 128 \gls{bit}s} } \newglossaryentry{HighOrderBits} { name={high order bits}, - description={Some number of MSBs} + description={Some number of \acrshort{msb}s} } \newglossaryentry{LowOrderBits} { name={low order bits}, - description={Some number of LSBs} + description={Some number of \acrshort{lsb}s} } \newglossaryentry{xlen} { name=XLEN, - description={The number of bits a RISC-V x integer register - (such as x0). For RV32 XLEN=32, RV64 XLEN=64 etc} + description={The number of bits a RISC-V x integer \gls{register} + (such as x0). For RV32 XLEN=32, RV64 XLEN=64 and so on} } \newglossaryentry{rv32} { name=RV32, - description={Short for RISC-V 32. The number 32 refers to the XLEN} + description={Short for RISC-V 32. The number 32 refers to the \gls{xlen}} } \newglossaryentry{rv64} { name=RV64, - description={Short for RISC-V 64. The number 64 refers to the XLEN} + description={Short for RISC-V 64. The number 64 refers to the \gls{xlen}} } \newglossaryentry{overflow} { @@ -101,12 +107,12 @@ { name={machine language}, description={The instructions that are executed by a CPU that are expressed - in the form of binary values} + in the form of \gls{binary} values} } \newglossaryentry{register} { name={register}, - description={A unit of storage inside a CPU with the capacity of XLEN bits} + description={A unit of storage inside a CPU with the capacity of \gls{xlen} \gls{bit}s} } \newglossaryentry{program} { @@ -116,7 +122,7 @@ \newglossaryentry{address} { name={address}, - description={A numeric value used to uniquely identify each byte of main memory} + description={A numeric value used to uniquely identify each \gls{byte} of main memory} } \newglossaryentry{alignment} { @@ -139,7 +145,7 @@ name={big endian}, description={A number format where the most significant values are printed to the left of the lesser significant values. This is the - method that everyone used to write decimal numbers every day} + method that everyone uses to write decimal numbers every day} } \newglossaryentry{littleendian} { @@ -147,7 +153,7 @@ description={A number format where the least significant values are printed to the left of the more significant values. This is the opposite ordering that everyone learns in grade school when learning - how to count. For example a big endian number written as ``1234'' + how to count. For example a \gls{bigendian} number written as ``1234'' would be written in little endian form as ``4321''} } \newglossaryentry{rvddt} @@ -178,3 +184,5 @@ \newacronym{lsb}{LSB}{Least Significant Bit} \newacronym{isa}{ISA}{Instruction Set Architecture} \newacronym{cpu}{CPU}{Central Processing Unit} +\newacronym{ram}{RAM}{Random Access Memory} +\newacronym{rom}{ROM}{Read Only Memory} diff --git a/book/insnformats.tex b/book/insnformats.tex index 7d6d68b..4b9d545 100644 --- a/book/insnformats.tex +++ b/book/insnformats.tex @@ -534,6 +534,57 @@ +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + + +\newcommand\xTInsnStatement[4]{% + \parbox{3.5cm}{{\sffamily\large\bfseries #2}\\ + \tt#3}\hspace{5mm}\parbox{5cm}{\bfseries#1}\parbox{12cm}{#4}% +} + +\newcommand\TInsnStatement[4]{% + \begin{tabular}{lll} + \parbox[t]{3.5cm}{{\sffamily\large\bfseries #2}\\ + \tt#3} & \parbox[t]{5cm}{\bfseries #1} & \parbox[t]{12cm}{#4}\\ + \end{tabular} +} + +\newcommand\TDrawInsnTypeUPicture[5]{% + \TInsnStatement{#1}{#2}{#3}{#4}\\ + \DrawInsnTypeUTikz{#5}% +} + +\newcommand\TDrawInsnTypeJPicture[5]{% + \TInsnStatement{#1}{#2}{#3}{#4}\\ + \DrawInsnTypeJTikz{#5}% +} + +\newcommand\TDrawInsnTypeBPicture[5]{% + \TInsnStatement{#1}{#2}{#3}{#4}\\ + \DrawInsnTypeBTikz{#5}% +} + +\newcommand\TDrawInsnTypeIPicture[5]{% + \TInsnStatement{#1}{#2}{#3}{#4}\\ + \DrawInsnTypeITikz{#5}% +} +\newcommand\TDrawInsnTypeSPicture[5]{% + \TInsnStatement{#1}{#2}{#3}{#4}\\ + \DrawInsnTypeSTikz{#5}% +} +\newcommand\TDrawInsnTypeRPicture[5]{% + \TInsnStatement{#1}{#2}{#3}{#4}\\ + \DrawInsnTypeRTikz{#5}% +} + +\newcommand\TDrawInsnTypeRShiftPicture[5]{ + \TInsnStatement{#1}{#2}{#3}{#4}\\ + \DrawInsnTypeRShiftTikz{#5} +} + %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% diff --git a/book/insnsummary/chapter.tex b/book/insnsummary/chapter.tex new file mode 100644 index 0000000..9003d36 --- /dev/null +++ b/book/insnsummary/chapter.tex @@ -0,0 +1,346 @@ +\chapter{Instruction Set Summary} + +\enote{Once the RV32I section is re-factored, it may end up turning into this.} + +\TDrawInsnTypeUPicture +{Load Upper Immediate} +{lui rd, imm} +{lui t0, 3} +{\tt% +rd $\leftarrow$ pc + sx(imm<<1)\\ +pc $\leftarrow$ pc + 4} +{00000000000000000011001010110111} + +\TDrawInsnTypeUPicture +{Add Upper Immediate PC} +{auipc rd, imm} +{auipc t0, 3} +{\tt% +rd $\leftarrow$ pc + zr(imm)\\ +pc $\leftarrow$ pc + 4} +{000000000000000000110010101xxxxx} + +\TDrawInsnTypeJPicture +{Jump And Link} +{jal rd, imm} +{jal x7, .+16} +{\tt% +rd $\leftarrow$ pc + 4\\ +pc $\leftarrow$ pc + sx(imm<<1)} +{00000001000000000000001111101111} + +\TDrawInsnTypeIPicture +{Jump And Link Register} +{jalr rd, rs1, imm} +{jalr x1, x7, 4} +{\tt% +rd $\leftarrow$ pc + 4\\ +pc $\leftarrow$ (rs1 + sx(imm)) \& \textasciitilde{}1} +{00000000010000111000000011100111} + +\enote{These branches (and likely other insns) are not encoded properly!} +\TDrawInsnTypeBPicture +{Branch Equal} +{beq rs1, rs2, imm} +{beq x3, x15, 2064} +{\tt pc $\leftarrow$ (rs1==rs2) ? pc+sx(imm[12:1]<<1) : pc+4} +{00000000111100011000100011100011} + +\TDrawInsnTypeBPicture +{Branch Not Equal} +{bne rs1, rs2, imm} +{bne x3, x15, 2064} +{\tt pc $\leftarrow$ (rs1!=rs2) ? pc+sx(imm[12:1]<<1) : pc+4} +{00000000111100011001100011100011} + +\TDrawInsnTypeBPicture +{Branch Less Than} +{blt rs1, rs2, imm} +{blt x3, x15, 2064} +{\tt pc $\leftarrow$ (rs1=rs2) ? pc+sx(imm[12:1]<<1) : pc+4} +{00000000111100011101100011100011} + +\TDrawInsnTypeBPicture +{Branch Less Than Unsigned} +{bltu rs1, rs2, imm} +{bltu x3, x15, 2064} +{\tt pc $\leftarrow$ (rs1=rs2) ? pc+sx(imm[12:1]<<1) : pc+4} +{00000000111100011111100011100011} + +\TDrawInsnTypeIPicture +{Load Byte} +{lb rd, imm(rs1)} +{lb x7, 4(x3)} +{\tt% +rd $\leftarrow$ sx(m8(rs1+sx(imm)))\\ +pc $\leftarrow$ pc+4} +{00000000010000011000001110000011} + +\TDrawInsnTypeIPicture +{Load Halfword} +{lh rd, imm(rs1)} +{lh x7, 4(x3)} +{\tt% +rd $\leftarrow$ sx(m16(rs1+sx(imm)))\\ +pc $\leftarrow$ pc+4} +{00000000010000011001001110000011} + +\TDrawInsnTypeIPicture +{Load Word} +{lw rd, imm(rs1)} +{lw x7, 4(x3)} +{\tt% +rd $\leftarrow$ sx(m32(rs1+sx(imm)))\\ +pc $\leftarrow$ pc+4} +{00000000010000011010001110000011} + +\TDrawInsnTypeIPicture +{Load Byte Unsigned} +{lbu rd, imm(rs1)} +{lbu x7, 4(x3)} +{\tt% +rd $\leftarrow$ zx(m8(rs1+sx(imm)))\\ +pc $\leftarrow$ pc+4} +{00000000010000011100001110000011} + +\TDrawInsnTypeIPicture +{Load Halfword Unsigned} +{lhu rd, imm(rs1)} +{lhu x7, 4(x3)} +{\tt% +rd $\leftarrow$ zx(m16(rs1+sx(imm)))\\ +pc $\leftarrow$ pc+4} +{00000000010000011101001110000011} + +\TDrawInsnTypeSPicture +{Store Byte} +{sb rs2, imm(rs1)} +{sb x3, 19(x15)} +{\tt% +m8(rs1+sx(imm)) $\leftarrow$ rs2[7:0]\\ +pc $\leftarrow$ pc+4} +{00000000111100011000100110100011} + +\TDrawInsnTypeSPicture +{Store Halfword} +{sh rs2, imm(rs1)} +{sh x3, 19(x15)} +{\tt% +m16(rs1+sx(imm)) $\leftarrow$ rs2[15:0]\\ +pc $\leftarrow$ pc+4} +{00000000111100011001100110100011} + +\TDrawInsnTypeSPicture +{Store Word} +{sw rs2, imm(rs1)} +{sw x3, 19(x15)} +{\tt% +m16(rs1+sx(imm)) $\leftarrow$ rs2[31:0]\\ +pc $\leftarrow$ pc+4} +{00000000111100011010100110100011} + +\TDrawInsnTypeIPicture +{Add Immediate} +{addi rd, rs1, imm} +{addi x1, x7, 4} +{\tt% +rd $\leftarrow$ rs1+sx(imm)\\ +pc $\leftarrow$ pc+4} +{00000000010000111000000010010011} + +\TDrawInsnTypeIPicture +{Set Less Than Immediate} +{slti rd, rs1, imm} +{slti x1, x7, 4} +{\tt% +rd $\leftarrow$ (rs1 < sx(imm)) ? 1 : 0\\ +pc $\leftarrow$ pc+4} +{00000000010000111010000010010011} + +\TDrawInsnTypeIPicture +{Set Less Than Immediate Unsigned} +{sltiu rd, rs1, imm} +{sltiu x1, x7, 4} +{\tt% +rd $\leftarrow$ (rs1 < sx(imm)) ? 1 : 0\\ +pc $\leftarrow$ pc+4} +{00000000010000111011000010010011} + +\TDrawInsnTypeIPicture +{Exclusive Or Immediate} +{xori rd, rs1, imm} +{xori x1, x7, 4} +{\tt% +rd $\leftarrow$ rs1 \^{} sx(imm)\\ +pc $\leftarrow$ pc+4} +{00000000010000111100000010010011} + +\TDrawInsnTypeIPicture +{Or Immediate} +{ori rd, rs1, imm} +{ori x1, x7, 4} +{\tt% +rd $\leftarrow$ rs1 | sx(imm)\\ +pc $\leftarrow$ pc+4} +{00000000010000111110000010010011} + +\TDrawInsnTypeIPicture +{And Immediate} +{andi rd, rs1, imm} +{andi x1, x7, 4} +{\tt% +rd $\leftarrow$ rs1 \& sx(imm)\\ +pc $\leftarrow$ pc+4} +{00000000010000111111000010010011} + + +\TDrawInsnTypeRShiftPicture +{Shift Left Logical Immediate} +{slli rd, rs1, shamt} +{slli x7, x3, 2} +{\tt% +rd $\leftarrow$ rs1 << shamt\\ +pc $\leftarrow$ pc+4} +{00000000001000011001001110100011} + + +\TDrawInsnTypeRShiftPicture +{Shift Right Logical Immediate} +{srli rd, rs1, shamt} +{srli x7, x3, 2} +{\tt% +rd $\leftarrow$ rs1 >> shamt\\ +pc $\leftarrow$ pc+4} +{00000000001000011101001110010011} + +\TDrawInsnTypeRShiftPicture +{Shift Right Arithmetic Immediate} +{srai rd, rs1, shamt} +{srai x7, x3, 2} +{\tt% +rd $\leftarrow$ rs1 >> shamt\\ +pc $\leftarrow$ pc+4} +{01000000001000011101001110010011} + +\TDrawInsnTypeRPicture +{Add} +{add rd, rs1, rs2} +{add x7, x3, x31} +{\tt% +rd $\leftarrow$ rs1 + rs2\\ +pc $\leftarrow$ pc+4} +{00000001111100011000001110110011} + +\TDrawInsnTypeRPicture +{Subtract} +{sub rd, rs1, rs2} +{SUB x7, x3, x31} +{\tt% +rd $\leftarrow$ rs1 - rs2\\ +pc $\leftarrow$ pc+4} +{01000001111100011000001110110011} + +\TDrawInsnTypeRPicture +{Shift Left Logical} +{sll rd, rs1, rs2} +{sll x7, x3, x31} +{\tt% +rd $\leftarrow$ rs1 << rs2\\ +pc $\leftarrow$ pc+4} +{00000001111100011001001110110011} + +\TDrawInsnTypeRPicture +{Set Less Than} +{slt rd, rs1, rs2} +{slt x7, x3, x31} +{\tt% +rd $\leftarrow$ rs1 < rs2) ? 1 : 0\\ +pc $\leftarrow$ pc+4} +{00000001111100011010001110110011} + +\TDrawInsnTypeRPicture +{Set Less Than Unsigned} +{sltu rd, rs1, rs2} +{sltu x7, x3, x31} +{\tt% +rd $\leftarrow$ (rs1 < rs2) ? 1 : 0\\ +pc $\leftarrow$ pc+4} +{00000001111100011011001110110011} + +\TDrawInsnTypeRPicture +{Exclusive Or} +{xor rd, rs1, rs2} +{xor x7, x3, x31} +{\tt% +rd $\leftarrow$ rs1 \^{} rs2\\ +pc $\leftarrow$ pc+4} +{00000001111100011100001110110011} + +\TDrawInsnTypeRPicture +{Shift Right Logical} +{srl rd, rs1, rs2} +{srl x7, x3, x31} +{\tt% +rd $\leftarrow$ rs1 >> rs2\\ +pc $\leftarrow$ pc+4} +{00000001111100011101001110110011} + +\TDrawInsnTypeRPicture +{Shift Right Arithmetic} +{sra rd, rs1, rs2} +{sra x7, x3, x31} +{\tt% +rd $\leftarrow$ rs1 >> rs2\\ +pc $\leftarrow$ pc+4} +{01000001111100011101001110110011} + +\TDrawInsnTypeRPicture +{Or} +{or rd, rs1, rs2} +{or x7, x3, x31} +{\tt% +rd $\leftarrow$ rs1 | rs2\\ +pc $\leftarrow$ pc+4} +{00000001111100011101001110110011} + +\TDrawInsnTypeRPicture +{And} +{and rd, rs1, rs2} +{and x7, x3, x31} +{\tt% +rd $\leftarrow$ rs1 \& rs2\\ +pc $\leftarrow$ pc+4} +{00000001111100011110001110110011} + +%\DrawInsnTypeFPicture{FENCE iorw, iorw}{00001111111100000000000000001111} +%\DrawInsnTypeFPicture{FENCE.I}{00000000000000000001000000001111} +%\DrawInsnTypeEPicture{ECALL}{00000000000000000000000001110011} +%\DrawInsnTypeEPicture{EBREAK}{00000000000100000000000001110011} +%\DrawInsnTypeCSPicture{CSRRW x3, 2, x15}{00000000001001111001000111110011} +%\DrawInsnTypeCSPicture{CSRRS x3, 2, x15}{00000000001001111010000111110011} +%\DrawInsnTypeCSPicture{CSRRC x3, 2, x15}{00000000001001111011000111110011} +%\DrawInsnTypeCSIPicture{CSRRWI x3, 2, 7}{00000000001000111101000111110011} +%\DrawInsnTypeCSIPicture{CSRRSI x3, 2, 7}{00000000001000111110000111110011} +%\DrawInsnTypeCSIPicture{CSRRCI x3, 2, 7}{00000000001000111111000111110011} +%\DrawInsnTypeRPicture{MUL x7, x3, x31}{00000011111100111000001110110011} +%\DrawInsnTypeRPicture{MULH x7, x3, x31}{00000011111100111001001110110011} +%\DrawInsnTypeRPicture{MULHS x7, x3, x31}{00000011111100111010001110110011} +%\DrawInsnTypeRPicture{MULHU x7, x3, x31}{00000011111100111011001110110011} +%\DrawInsnTypeRPicture{DIV x7, x3, x31}{00000011111100111100001110110011} +%\DrawInsnTypeRPicture{DIVU x7, x3, x31}{00000011111100111101001110110011} +%\DrawInsnTypeRPicture{REM x7, x3, x31}{00000011111100111110001110110011} +%\DrawInsnTypeRPicture{REMU x7, x3, x31}{00000011111100111111001110110011} diff --git a/book/intro/chapter.tex b/book/intro/chapter.tex index 9154fcf..57930f6 100644 --- a/book/intro/chapter.tex +++ b/book/intro/chapter.tex @@ -50,7 +50,8 @@ small blocks called \glspl{register}. These registers are used to hold individual data values that can be manipulated by the instructions that are executed by the CPU. -Another type of volatile storage is main memory. +Another type of volatile storage is main memory +(sometimes called \acrshort{ram}) Main memory is connected to a computer's CPU and is used to hold the data and instructions that can not fit into the CPU registers. @@ -78,7 +79,8 @@ the registers and main memory is a desirable trait of good programs. Non-volatile storage is characterized by the fact that it will {\em NOT} lose its contents when it is powered off. -Common types of non-volatile storage are disc drives, flash cards and USB +Common types of non-volatile storage are disc drives, +\acrshort{rom} flash cards and USB drives. Prices can vary widely depending on size and transfer speeds. It is typical for a computer system's non-volatile storage to operate diff --git a/book/refcard/chapter.tex b/book/refcard/chapter.tex new file mode 100644 index 0000000..a70fb4f --- /dev/null +++ b/book/refcard/chapter.tex @@ -0,0 +1,81 @@ +\chapter{RV32I Reference Card} + + +\begin{tabular}{|ll|l|l|} +\hline +lui & t0, 3 & Load Upper Immediate & {\tt rd $\leftarrow$ zr(imm), pc $\leftarrow$ pc+4}\\ +\hline +auipc & t0, 3 & Add Upper Immediate to PC & {\tt rd $\leftarrow$ pc + zr(imm), pc $\leftarrow$ pc+4}\\ +\hline +jal & rd, imm & Jump And Link & {\tt{}rd $\leftarrow$ pc+4, pc $\leftarrow$ pc+sx(imm<<1)}\\ +\hline +jalr & rd, rs1, imm & Jump And Link Register & {\tt{}rd $\leftarrow$ pc+4, pc $\leftarrow$ (rs1+sx(imm))\&\textasciitilde{}1}\\ +\hline +beq & rs1, rs2, imm & Branch Equal & {\tt{}pc $\leftarrow$ \verb@(rs1==rs2) ? pc+sx(imm[12:1]<<1) : pc+4@}\\ +\hline +bne & rs1, rs2, imm & Branch Not Equal & {\tt pc $\leftarrow$ (rs1!=rs2) ? pc+sx(imm[12:1]<<1) : pc+4}\\ +\hline +blt & rs1, rs2, imm & Branch Less Than & {\tt pc $\leftarrow$ (rs1=rs2) ? pc+sx(imm[12:1]<<1) : pc+4}\\ +\hline +bltu & rs1, rs2, imm & Branch Less Than Unsigned & {\tt pc $\leftarrow$ (rs1=rs2) ? pc+sx(imm[12:1]<<1) : pc+4}\\ +\hline +lb & rd, imm(rs1) & Load Byte & {\tt rd $\leftarrow$ sx(m8(rs1+sx(imm))), pc $\leftarrow$ pc+4}\\ +\hline +lh & rd, imm(rs1) & Load Halfword & {\tt rd $\leftarrow$ sx(m16(rs1+sx(imm))), pc $\leftarrow$ pc+4}\\ +\hline +lw & rd, imm(rs1) & Load Word & {\tt rd $\leftarrow$ sx(m32(rs1+sx(imm))), pc $\leftarrow$ pc+4}\\ +\hline +lbu & rd, imm(rs1) & Load Byte Unsigned & {\tt rd $\leftarrow$ zx(m8(rs1+sx(imm))), pc $\leftarrow$ pc+4}\\ +\hline +lhu & rd, imm(rs1) & Load Halfword Unsigned & {\tt rd $\leftarrow$ zx(m16(rs1+sx(imm))), pc $\leftarrow$ pc+4}\\ +\hline +sb & rs2, imm(rs1) & Store Byte & {\tt m8(rs1+sx(imm)) $\leftarrow$ rs2[7:0], pc $\leftarrow$ pc+4}\\ +\hline +sh & rs2, imm(rs1) & Store Halfword & {\tt m16(rs1+sx(imm)) $\leftarrow$ rs2[15:0], pc $\leftarrow$ pc+4}\\ +\hline +sw & rs2, imm(rs1) & Store Word & {\tt m16(rs1+sx(imm)) $\leftarrow$ rs2[31:0], pc $\leftarrow$ pc+4}\\ +\hline +addi & rd, rs1, imm & Add Immediate & {\tt rd $\leftarrow$ rs1+sx(imm), pc $\leftarrow$ pc+4}\\ +\hline +slti & rd, rs1, imm & Set Less Than Immediate & {\tt rd $\leftarrow$ (rs1 < sx(imm)) ? 1 : 0, pc $\leftarrow$ pc+4}\\ +\hline +sltiu & rd, rs1, imm & Set Less Than Immediate Unsigned & {\tt rd $\leftarrow$ (rs1 < sx(imm)) ? 1 : 0, pc $\leftarrow$ pc+4}\\ +\hline +xori & rd, rs1, imm & Exclusive Or Immediate & {\tt rd $\leftarrow$ rs1 \^{} sx(imm), pc $\leftarrow$ pc+4}\\ +\hline +ori & rd, rs1, imm & Or Immediate & {\tt rd $\leftarrow$ rs1 | sx(imm), pc $\leftarrow$ pc+4}\\ +\hline +andi & rd, rs1, imm & And Immediate & {\tt rd $\leftarrow$ rs1 \& sx(imm), pc $\leftarrow$ pc+4}\\ +\hline +slli & rd, rs1, shamt & Shift Left Logical Immediate & {\tt rd $\leftarrow$ rs1 << shamt, pc $\leftarrow$ pc+4}\\ +\hline +srli & rd, rs1, shamt & Shift Right Logical Immediate & {\tt rd $\leftarrow$ rs1 >> shamt, pc $\leftarrow$ pc+4}\\ +\hline +srai & rd, rs1, shamt & Shift Right Arithmetic Immediate & {\tt rd $\leftarrow$ rs1 >> shamt, pc $\leftarrow$ pc+4}\\ +\hline +add & rd, rs1, rs2 & Add & {\tt rd $\leftarrow$ rs1 + rs2, pc $\leftarrow$ pc+4}\\ +\hline +sub & rd, rs1, rs2 & Subtract & {\tt rd $\leftarrow$ rs1 - rs2, pc $\leftarrow$ pc+4}\\ +\hline +sll & rd, rs1, rs2 & Shift Left Logical & {\tt rd $\leftarrow$ rs1 << rs2, pc $\leftarrow$ pc+4}\\ +\hline +slt & rd, rs1, rs2 & Set Less Than & {\tt rd $\leftarrow$ rs1 < rs2) ? 1 : 0, pc $\leftarrow$ pc+4}\\ +\hline +sltu & rd, rs1, rs2 & Set Less Than Unsigned & {\tt rd $\leftarrow$ (rs1 < rs2) ? 1 : 0, pc $\leftarrow$ pc+4}\\ +\hline +xor & rd, rs1, rs2 & Exclusive Or & {\tt rd $\leftarrow$ rs1 \^{} rs2, pc $\leftarrow$ pc+4}\\ +\hline +srl & rd, rs1, rs2 & Shift Right Logical & {\tt rd $\leftarrow$ rs1 >> rs2, pc $\leftarrow$ pc+4}\\ +\hline +sra & rd, rs1, rs2 & Shift Right Arithmetic & {\tt rd $\leftarrow$ rs1 >> rs2, pc $\leftarrow$ pc+4}\\ +\hline +or & rd, rs1, rs2 & Or & {\tt rd $\leftarrow$ rs1 | rs2, pc $\leftarrow$ pc+4}\\ +\hline +and & rd, rs1, rs2 & And & {\tt rd $\leftarrow$ rs1 \& rs2, pc $\leftarrow$ pc+4}\\ +\hline +\end{tabular} + diff --git a/book/rv32/chapter.tex b/book/rv32/chapter.tex index f40c2d7..c83c13c 100644 --- a/book/rv32/chapter.tex +++ b/book/rv32/chapter.tex @@ -27,37 +27,8 @@ This is used to convert a signed integer value expressed using some number of bits to a larger number of bits by adding more bits to the left. In doing so, the sign will be preserved. In this case {\em val} represents the least \acrshort{msb}s of the value. -For more on binary numbers see \autoref{chapter:NumberSystems}. - -\autoref{Figure:SignExtendNegative} illustrates extending the negative sign -bit of {\em val} to the left by replicating it. -When {\em val} is negative, its \acrshort{msb} (bit 19 in this example) will -be set to 1. Extending this value to the left will set all the new bits -to the left of it to 1 as well. - - -\begin{figure}[ht] -\centering -\DrawBitBoxSignExtendedPicture{32}{10100000000000000010} -\captionof{figure}{Sign-extending a negative integer from 20 bits to 32 bits.} -\label{Figure:SignExtendNegative} -\end{figure} - - -\autoref{Figure:SignExtendPositive} illustrates extending the positive sign -bit of {\em val} to the left by replicating it. -When {\em val} is positive, its \acrshort{msb} will be set to 0. Extending this -value to the left will set all the new bits to the left of it to 0 as well. - - -\begin{figure}[ht] -\centering -\DrawBitBoxSignExtendedPicture{32}{01000000000000000010} -\captionof{figure}{Sign-extending a positive integer from 20 bits to 32 bits.} -\label{Figure:SignExtendPositive} -\end{figure} - +For more on sign-extension see \autoref{SignExtension}. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{zx(val)} @@ -69,19 +40,8 @@ This is used to convert an unsigned integer value expressed using some number of bits to a larger number of bits by adding more bits to the left. In doing so, the new bits added will all be set to zero. As is the case with \verb@sx(val)@, {\em val} represents the \acrshort{lsb}s of the final value. -\autoref{Figure:ZeroExtend} illustrates zero-extending a 20-bit {\em val} to the -left to form a 32-bit fullword. - -For more on binary numbers see \autoref{chapter:NumberSystems}. - -\begin{figure}[ht] -\centering -\DrawBitBoxZeroExtendedPicture{32}{10000000000000000010} -\captionof{figure}{Zero-extending an unsigned integer from 20 bits to 32 bits.} -\label{Figure:ZeroExtend} -\end{figure} - +For more on zero-extension see \autoref{ZeroExtension}. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% @@ -556,6 +516,8 @@ atomically.~\cite[p.19]{rvismv1v22:2017} See also \autoref{RV32A}. \section{RV32I Base Instruction Set} \index{RV32I} +\enote{Migrate all te details into the programming chapter and +reduce this section to the obligatory reference chapter.}% \Gls{rv32}I refers to the basic 32-bit integer instructions. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% @@ -1400,7 +1362,7 @@ register rs2.~\cite[p.~14,~15]{rvismv1v22:2017} Encoding: -\DrawInsnTypeRPicture{SLA x7, x3, x31}{01000001111100011101001110110011} +\DrawInsnTypeRPicture{SRA x7, x3, x31}{01000001111100011101001110110011} x3 = 0x83333333\\ x31 = 0x00000010 diff --git a/releases/rvalp-v0.1-19-g15586ff.pdf b/releases/rvalp-v0.1-19-g15586ff.pdf deleted file mode 100644 index 6ba4fb6..0000000 Binary files a/releases/rvalp-v0.1-19-g15586ff.pdf and /dev/null differ diff --git a/releases/rvalp-v0.1-26-ge892461.pdf b/releases/rvalp-v0.1-26-ge892461.pdf deleted file mode 100644 index 8d5a61d..0000000 Binary files a/releases/rvalp-v0.1-26-ge892461.pdf and /dev/null differ diff --git a/releases/rvalp-v0.1-36-g8be5378.pdf b/releases/rvalp-v0.1-36-g8be5378.pdf deleted file mode 100644 index 63b4b61..0000000 Binary files a/releases/rvalp-v0.1-36-g8be5378.pdf and /dev/null differ diff --git a/releases/rvalp-v0.1-61-gcaaa6b3.pdf b/releases/rvalp-v0.1-61-gcaaa6b3.pdf new file mode 100644 index 0000000..13e023e Binary files /dev/null and b/releases/rvalp-v0.1-61-gcaaa6b3.pdf differ