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8
book/glossary.tex
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@ -15,8 +15,8 @@
\newglossaryentry{hexadecimal}
{
name=hexadecimal,
description={A base--16 numbering system whose digits are
0123456789abcdef. The hex digits (hits) are not case--sensitive}
description={A base-16 numbering system whose digits are
0123456789abcdef. The hex digits (hits) are not case-sensitive}
}
\newglossaryentry{bit}
{
@ -86,7 +86,7 @@
description={The situation where the result of an addition or
subtraction operation is approaching positive or negative
infinity and exceeds the number of bits alloted to contain
the result. This is typically caused by high--order truncation}
the result. This is typically caused by high-order truncation}
}
\newglossaryentry{underflow}
{
@ -94,7 +94,7 @@
description={The situation where the result of an addition or
subtraction operation is approaching zero and exceeds the number
of bits alloted to contain the result. This is typically
caused by low--order truncation}
caused by low-order truncation}
}
\newglossaryentry{MachineLanguage}

44
book/intro/chapter.tex
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@ -36,7 +36,7 @@ Computer storage systems are used to hold the data and instructions
for the CPU.
Types of computer storage can be classified into two categories.
Volatile and non--volatile.
Volatile and non-volatile.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsubsection{Volatile Storage}
@ -68,18 +68,18 @@ in its main memory. As a result, optimizing the copying of data between
the registers and main memory is a desirable trait of good programs.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsubsection{Non--Volatile Storage}
\subsubsection{Non-Volatile Storage}
Non--volatile storage is characterized by the fact that it will {\em NOT}
Non-volatile storage is characterized by the fact that it will {\em NOT}
lose its contents when it is powered off.
Common types of non--volatile storage are disc drives, flash cards and USB
Common types of non-volatile storage are disc drives, flash cards and USB
drives. Prices can vary widely depending on size and transfer speeds.
It is typical for a computer system's non--volatile storage to operate
It is typical for a computer system's non-volatile storage to operate
more slowly than its main memory.
This text is not particularly concerned with non--volatile storage.
This text is not particularly concerned with non-volatile storage.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{CPU}
@ -115,23 +115,23 @@ An ISA is typically expressed in terms of the specific meaning of
each binary instruction that a CPU can recognize and how it will
process each one.
The RISC--V ISA is defined as a set of modules. The purpose of
The RISC-V ISA is defined as a set of modules. The purpose of
dividing the ISA into modules is to allow an implementor to select which
features to incorporate into a CPU design.
Any given RISC--V implementation must provide one of the {\em base}
Any given RISC-V implementation must provide one of the {\em base}
modules and zero or more of the {\em extension} modules.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{RV Base Modules}
\index{RV32I}
The base modules are RV32I (32--bit general purpose),
RV32E (32--bit embedded), RV64I (64--bit general purpose)
and RV128I (128--bit general purpose).
The base modules are RV32I (32-bit general purpose),
RV32E (32-bit embedded), RV64I (64-bit general purpose)
and RV128I (128-bit general purpose).
These base modules provide the minimal functional set of integer operations
needed to execute an application. The differing bit--widths address
the needs of different main--memory sizes.
needed to execute an application. The differing bit-widths address
the needs of different main-memory sizes.
This text primairly focuses on the RV32I base module and how to program it.
@ -149,8 +149,8 @@ RISC-V extension modules may be included by an implementor interested
in optimizing a design for one or more purposes.
Available extension modules include M (integer math), A (atomic),
F (32--bit floating point), D (64--bit floating point),
Q (128--bit floating point), C (compressed size instructions) and others.
F (32-bit floating point), D (64-bit floating point),
Q (128-bit floating point), C (compressed size instructions) and others.
The extension name {\em G} is used to represent the combined set of IMAFD
extensions as it is expected to be a common combination.
@ -174,14 +174,14 @@ and 65536 bytes of memory.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\section{An Example Program}
\section{Executing a Program}
To observe the operation of our example computer an RV32I simulator
will be used that will print a message describing the status of the
CPU and the instructions that it executes as it goes along.
The process of executing an instruction is called the
\index{instruction cycle} instruction cycle and it is comprised
The process of executing an instruction is called an
\index{instruction cycle}{\em instruction cycle} and it is comprised
of an {\em instruction fetch} and an {\em instruction execute} phase.
The status of the CPU is entirely embodied in the data values that
@ -203,6 +203,7 @@ or read from (or stored into) one or more of the registers.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Instruction Fetch}
\index{instruction fetch}
In order to {\em fetch} an instruction from the main memory the CPU
must have a method to identify which instruction should be fetched and
@ -252,6 +253,7 @@ See~\cite{codriscv:2017} for more information on computer organization.}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Instruction Execute}
\index{instruction execute}
Once an instruction has been fetched by the CPU, it can be executed.
@ -335,7 +337,7 @@ This program listing illustrates a number of things:
will always contain the vlaue zero. It can never be changed.)
\item [0] The second addend is the number zero.
\item [\# set \ldots] Any text anywhere in a RISC-V assembly language
program that starts with the pound--sign is ignored by the assembler.
program that starts with the pound-sign is ignored by the assembler.
They are used to place a {\em comment} in the program to help
the reader better understand the motive of the programmer.
\end{itemize}
@ -378,7 +380,7 @@ is less than 1700 lines of C++ and was written in one (long) afternoon.}
It contains the address of the instruction that the CPU will execute.
After each instruction, the \reg{pc} will either advance four bytes
ahead or be set to another value by a branch instruction as discussed above.
\item [$\ell$ 9] A four--byte instruction is fetched from memory at the address
\item [$\ell$ 9] A four-byte instruction is fetched from memory at the address
in the \reg{pc} register, is decoded and printed. From left to right
the fields shown on this line are:
@ -395,7 +397,7 @@ is less than 1700 lines of C++ and was written in one (long) afternoon.}
holds one of the two addends of the operation.
\item [0] The \reg{imm} field of the addi instruction that
holds the second of the two addends of the operation.
\item [\# \ldots] A simulator--generated comment that exaplains
\item [\# \ldots] A simulator-generated comment that exaplains
what the instruction is doing. For this instruction it indicates
that \reg{x28} will have the value zero stored into it as a result
of performing the addition: $0+0$.

6
book/license/chapter.tex
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@ -32,16 +32,16 @@ exhaustive, and do not form part of our licenses.
applying our licenses so that the public can reuse the
material as expected. Licensors should clearly mark any
material not subject to the license. This includes other
CC--licensed material, or material used under an exception or
CC-licensed material, or material used under an exception or
limitation to copyright. More considerations for licensors:
\url{http://wiki.creativecommons.org/Considerations_for_licensors}
Considerations for the public: By using one of our public
licenses, a licensor grants the public permission to use the
licensed material under specified terms and conditions. If
the licensor's permission is not necessary for any reason--for
the licensor's permission is not necessary for any reason-for
example, because of any applicable exception or limitation to
copyright--then that use is not regulated by the license. Our
copyright-then that use is not regulated by the license. Our
licenses grant only permissions under copyright and certain
other rights that a licensor has authority to grant. Use of
the licensed material may still be restricted for other

52
book/numbers/chapter.tex
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@ -60,7 +60,7 @@ $10^2$ & $10^1$ & $10^0$ & $2^7$ & $2^6$ & $2^5$ & $2^4$ & $2^3$ & $2^2$ & $2^1$
\end{figure}
One way to look at this table is on a per--row basis where each place
One way to look at this table is on a per-row basis where each place
value is represented by the base raised to the power of the place value
position (shown in the column headings.) This is useful when
converting arbitrary values between bases. For example to interpret
@ -72,9 +72,9 @@ And the same for the hexadecimal value:
\[ 0 \times 16^1 + 3 \times 16^0 = 3_{10} \]
Another way to look at this table is on a per--column basis. When
Another way to look at this table is on a per-column basis. When
tasked with drawing such a table by hand, it might be useful
to observe that, just as in decimal, the right--most column will
to observe that, just as in decimal, the right-most column will
cycle through all of the values represented in the chosen base
then cycle back to zero and repeat. (For example, in binary this
pattern is 0-1-0-1-0-1-0-\ldots) The next column in each base
@ -138,7 +138,7 @@ To convert from binary to decimal, put the decimal value of the place values
0 0 0 1 1 0 1 1
\end{verbatim}
Now sum the place--values that are expressed in decimal for each
Now sum the place-values that are expressed in decimal for each
bit with the value of 1: $16+8+2+1$. The integer binary value
$00011011_2$ represents the decimal value $27_{10}$.
@ -162,7 +162,7 @@ Decimal: 4+2 =6 8+4+ 1=13 8+ 2 =10 8+4+2 =14
After the summing, convert each decimal value to hex. The decimal
values from 0--9 are the same values in hex. Because we don't have any
more numerals to represent the values from 10-15, we use the first 6
letters (See the right--most column of \autoref{Figure:integers}.)
letters (See the right-most column of \autoref{Figure:integers}.)
Fortunately there are only six hex mappings involving letters. Thus
it is reasonable to memorize them.
@ -178,13 +178,13 @@ Hex: 6 D A E
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsubsection{From Hexadecimal to Binary}
Again, the four--bit mapping between binary and hex makes this
Again, the four-bit mapping between binary and hex makes this
task as straight forward as using a look-up table.
For each \gls{hit} (Hex digIT), translate it to its unique four--bit pattern.
For each \gls{hit} (Hex digIT), translate it to its unique four-bit pattern.
Perform this task either by memorizing each of the 16 patterns
or by converting each hit to decimal first and then converting
each four--bit binary value to decimal using the place--value summing
each four-bit binary value to decimal using the place-value summing
method discussed in \autoref{section:bindec}.
For example:
@ -233,7 +233,7 @@ the \acrshort{lsb} on the bottom line: $010011010010_2$.
\subsubsection{From Decimal to Hex}
Conversion from decimal to hex can be done by using the place
values for base--16 and the same math as from decimal to binary
values for base-16 and the same math as from decimal to binary
or by first converting the decimal value to binary and then
from binary to hex by using the methods discussed above.
@ -245,7 +245,7 @@ a conversion by way of binary is quite straight forward.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Addition of Binary Numbers}
The addition of binary numbers can be performed long--hand the
The addition of binary numbers can be performed long-hand the
same way decimal addition is taught in grade school. In fact binary
addition is easier since it only involves adding 0 or 1.
@ -372,7 +372,7 @@ signed and unsigned numbers.
\enote{This section needs more examples of subtracting
signed an unsigned numbers and a discussion on how
signedness is not relevant until the results are interpreted.
For example adding $-4+ -8=-12$ using two 8--bit numbers
For example adding $-4+ -8=-12$ using two 8-bit numbers
is the same as adding $252+248=500$ and truncating the result
to 244.}
@ -413,10 +413,10 @@ addition and subtraction.}
\subsection{Logical/Boolean Functions}
Unlike addition and subtraction, boolean functions apply
on a per--bit basis.
on a per-bit basis.
%in that they do not impact neighboring bits.
%by generating things like a carry or a borrow.
When applied to multi--bit values, each bit position is operated upon
When applied to multi-bit values, each bit position is operated upon
independantly of the other bits.
\enote{This is unclear. Need to define bit positions and probably
should add basic truth table diagrams.}
@ -562,9 +562,9 @@ needed to represent the entire, exact, value of a number.
\item In binary we have $mantissa \times 2^{exponent}$
\item IEEE--754 format requires binary numbers to be {\em normalized} to
\item IEEE-754 format requires binary numbers to be {\em normalized} to
$1.significand \times 2^{exponent}$ where the {\em significand}
is the portion of the {\em mantissa} that is to the right of the binary--point.
is the portion of the {\em mantissa} that is to the right of the binary-point.
\begin{itemize}
\item The unnormalized binary value of $-2.625$ is $10.101$
@ -643,10 +643,10 @@ normalized values by adding 1 to the significand.
\begin{tabular}{|l|l|l|}
\hline
& IEEE754 32--bit & IEEE754 64--bit \\
& IEEE754 32-bit & IEEE754 64-bit \\
\hline
sign & 1 bit & 1 bit \\
exponent & 8 bits (excess--127) & 11 bits (excess-1023) \\
exponent & 8 bits (excess-127) & 11 bits (excess-1023) \\
mantissa & 23 bits & 52 bits \\
max exponent & 127 & 1023 \\
min exponent & -126 & -1022 \\
@ -667,21 +667,21 @@ This is why we use excess notation and locate the significand's sign bit on
the left of the exponent.
\item Note that zero is a special case number. Recall that a normalized
number has an implied 1--bit to the left of the significand\ldots\ which
number has an implied 1-bit to the left of the significand\ldots\ which
means that there is no way to represent zero!
Zero is represented by an exponent of all--zeros and a significand of
all--zeros. This definition allows for a positive and a negative zero
Zero is represented by an exponent of all-zeros and a significand of
all-zeros. This definition allows for a positive and a negative zero
if we observe that the sign can be either 1 or 0.
\item On the number-line, numbers between zero and the smallest fraction in
either direction are in the {\em \gls{underflow}} areas.
\enote{Need to add the standard lecture numberline diagram showing
where the over/under--flow areas are and why.}
where the over/under-flow areas are and why.}
\item On the number line, numbers greater than the mantissa of all--ones and the
\item On the number line, numbers greater than the mantissa of all-ones and the
largest exponent allowed are in the {\em \gls{overflow}} areas.
\item Note that numbers have a higher resolution on the number--line when the
\item Note that numbers have a higher resolution on the number line when the
exponent is smaller.
\end{itemize}
@ -725,10 +725,10 @@ These rounding errors can be exaggerated when the number we multiply
the \verb@x.f@ value by is, itself, something that can not be accurately
represented in IEEE
form.\footnote{Applications requiring accurate decimal values, such as
financial accounting systems, can use a packed--decimal numeric format
financial accounting systems, can use a packed-decimal numeric format
to avoid unexpected oddities caused by the use of binary numbers.}
\enote{In a lecture one would show that one tenth is a repeating
non--terminating binary number that gets truncated. This discussion
non-terminating binary number that gets truncated. This discussion
should be reproduced here in text form.}
For example, if we multiply our \verb@x.f@ value by $\frac{1}{10}$ each time,
@ -743,7 +743,7 @@ In order to use floating point numbers in a program without causing
excessive rounding problems an algorithm can be redesigned such that the
accumulation is eliminated.
This example is similar to the previous one, but this time we recalculate the
desired value from a known--accurate integer value.
desired value from a known-accurate integer value.
Some rounding errors remain present, but they can not accumulate.
\listing{errorcompensation.c}{Accumulation of Error}

2
book/preface/chapter.tex
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@ -36,7 +36,7 @@ my shelves) such as:
\end{itemize}
One way or another all of them discuss each CPU instruction in excruciating detail
with both a logical and narrative description. For RISC--V this is
with both a logical and narrative description. For RISC-V this is
also the case for the {\em RISC-V Reader}\cite{riscvreader:2017} and the
{\em Computer Organization and Design RISC-V Edition}\cite{codriscv:2017} books
and is also present in this text (I consider that to be the minimal

122
book/rv32/chapter.tex
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@ -5,7 +5,7 @@
\section{Introduction}
\enote{Discuss what the IMAFD, G and other ISA extensions mean as well as the
32, 64 and 128--bit versions.}
32, 64 and 128-bit versions.}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
@ -17,7 +17,7 @@ When discussing instructions, the following abbreviations/notations are used:
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{XLEN}
XLEN represents the bit--length of an \reg{x} register in the machine architecture.
XLEN represents the bit-length of an \reg{x} register in the machine architecture.
Possible values are 32, 64 and 128.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
@ -42,7 +42,7 @@ to the left of it to 1 as well.
\begin{figure}[ht]
\centering
\DrawBitBoxSignExtendedPicture{32}{10100000000000000010}
\captionof{figure}{Sign--extending a negative integer from 20 bits to 32 bits.}
\captionof{figure}{Sign-extending a negative integer from 20 bits to 32 bits.}
\label{Figure:SignExtendNegative}
\end{figure}
@ -56,7 +56,7 @@ value to the left will set all the new bits to the left of it to 0 as well.
\begin{figure}[ht]
\centering
\DrawBitBoxSignExtendedPicture{32}{01000000000000000010}
\captionof{figure}{Sign--extending a positive integer from 20 bits to 32 bits.}
\captionof{figure}{Sign-extending a positive integer from 20 bits to 32 bits.}
\label{Figure:SignExtendPositive}
\end{figure}
@ -72,15 +72,15 @@ This is used to convert an unsigned integer value expressed using some number of
bits to a larger number of bits by adding more bits to the left. In doing so,
the new bits added will all be set to zero. As is the case with \verb@sx(val)@,
{\em val} represents the \acrshort{lsb}s of the final value.
\autoref{Figure:ZeroExtend} illustrates zero--extending a 20--bit {\em val} to the
left to form a 32--bit fullword.
\autoref{Figure:ZeroExtend} illustrates zero-extending a 20-bit {\em val} to the
left to form a 32-bit fullword.
For more on binary numbers see \autoref{chapter:NumberSystems}.
\begin{figure}[ht]
\centering
\DrawBitBoxZeroExtendedPicture{32}{10000000000000000010}
\captionof{figure}{Zero--extending an unsigned integer from 20 bits to 32 bits.}
\captionof{figure}{Zero-extending an unsigned integer from 20 bits to 32 bits.}
\label{Figure:ZeroExtend}
\end{figure}
@ -99,13 +99,13 @@ value.
In this case it is necessary to append zeros to the right to convert \verb@val@ to
the longer value.
\autoref{Figure:ZeroRightExtend} illustrates converting a 20--bit {\em val} to
a 32--bit fullword.
\autoref{Figure:ZeroRightExtend} illustrates converting a 20-bit {\em val} to
a 32-bit fullword.
\begin{figure}[ht]
\centering
\DrawBitBoxSignLeftZeroRightExtendedPicture{32}{01000000000000000010}{12}
\captionof{figure}{Zero--extending an integer to the right from 20 bits to 32 bits.}
\captionof{figure}{Zero-extending an integer to the right from 20 bits to 32 bits.}
\label{Figure:ZeroRightExtend}
\end{figure}
@ -115,7 +115,7 @@ a 32--bit fullword.
%\DrawBitBoxUnsignedPicture{01000000000000000010}\\
%\DrawBitBoxUnsignedPicture{01000000000000000010000000000000}
%}
%\captionof{figure}{Zero--extending an integer to the right from 20 bits to 32 bits.}
%\captionof{figure}{Zero-extending an integer to the right from 20 bits to 32 bits.}
%\label{Figure:ZeroRightExtend}
%\end{figure}
@ -124,17 +124,17 @@ a 32--bit fullword.
\subsection{Sign Entended Left and Zero Extend Right}
\label{extension:slzr}
Some instructions such as the J--type (see \autoref{insnformat:jtype}) include
Some instructions such as the J-type (see \autoref{insnformat:jtype}) include
immediate operands that are extended in both directions.
\autoref{Figure:slzrPositive} and \autoref{Figure:slzrNegative}
illustrates zero--extending a 20--bit negative number one bit to the right
and sign--extending it 11 bits to the left:
illustrates zero-extending a 20-bit negative number one bit to the right
and sign-extending it 11 bits to the left:
\begin{figure}[ht]
\centering
\DrawBitBoxSignLeftZeroRightExtendedPicture{32}{01000100011101001001}{1}
\captionof{figure}{Sign--extending a positive 20--bit number
\captionof{figure}{Sign-extending a positive 20-bit number
11 bits to the left and one bit to the right.}
\label{Figure:slzrPositive}
\end{figure}
@ -142,7 +142,7 @@ and sign--extending it 11 bits to the left:
\begin{figure}[ht]
\centering
\DrawBitBoxSignLeftZeroRightExtendedPicture{32}{11000100011101001001}{1}
\captionof{figure}{Sign--extending a negative 20--bit number
\captionof{figure}{Sign-extending a negative 20-bit number
11 bits to the left and one bit to the right.}
\label{Figure:slzrNegative}
\end{figure}
@ -152,12 +152,12 @@ and sign--extending it 11 bits to the left:
\subsection{m8(addr)}
\label{memory:m8}
The contents of an 8--bit value in memory at address {\em addr}.
The contents of an 8-bit value in memory at address {\em addr}.
Given the contents of the memory dump shown in
\autoref{Figure:SampleMemoryContents},
\verb@m8(42)@ refers to the memory location at address \verb@42@$_{16}$
that currently contains the 8--bit value \verb@fc@$_{16}$.
that currently contains the 8-bit value \verb@fc@$_{16}$.
The \verb@mn(addr)@ notation can be used to refer to memory that is being
read or written depending on the context.
@ -193,7 +193,7 @@ Note that {\em source} and {\em dest} are typically registers.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{m16(addr)}
The contents of an 16--bit little--endian value in memory at address {\em addr}.
The contents of an 16-bit little-endian value in memory at address {\em addr}.
Given the contents of the memory dump shown in
\autoref{Figure:SampleMemoryContents},
@ -204,7 +204,7 @@ that currently contains \verb@65fc@$_{16}$. See also~\autoref{memory:m8}.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{m32(addr)}
The contents of an 32--bit little--endian value in memory at address {\em addr}.
The contents of an 32-bit little-endian value in memory at address {\em addr}.
Given the contents of the memory dump shown in
\autoref{Figure:SampleMemoryContents},
@ -215,7 +215,7 @@ See also~\autoref{memory:m8}.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{m64(addr)}
The contents of an 64--bit little--endian value in memory at address {\em addr}.
The contents of an 64-bit little-endian value in memory at address {\em addr}.
Given the contents of the memory dump shown in
\autoref{Figure:SampleMemoryContents},
@ -226,7 +226,7 @@ See also~\autoref{memory:m8}.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{m128(addr)}
The contents of an 128--bit little--endian value in memory at
The contents of an 128-bit little-endian value in memory at
address {\em addr}.
Given the contents of the memory dump shown in
@ -253,17 +253,17 @@ The current value of the program counter.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{rd}
An x--register used to store the result of instruction.
An x-register used to store the result of instruction.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{rs1}
An x--register value used as a source operand for an instruction.
An x-register value used as a source operand for an instruction.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{rs2}
An x--register value used as a source operand for an instruction.
An x-register value used as a source operand for an instruction.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{imm}
@ -274,7 +274,7 @@ to the fact that the operand is stored within an instruction.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{rsN[h:l]}
The value of bits from {\em h} through {\em l} of x--register rsN.
The value of bits from {\em h} through {\em l} of x-register rsN.
For example: rs1[15:0] refers to the contents of
the 16 \acrshort{lsb}s of rs1.
@ -326,7 +326,7 @@ This simplification can also allow it operate faster.
\subsection{U Type}
\label{insnformat:utype}
The U--Type format is used for instructions that use a 20--bit immediate operand
The U-Type format is used for instructions that use a 20-bit immediate operand
and a destination register.
\DrawInsnTypeUTikz{11010110000000000011001010110111}
@ -335,9 +335,9 @@ The \reg{rd} field contains an \reg{x} register number to be set to a value that
depends on the instruction.
The imm field
contains a 20--bit value that will be converted into \Gls{xlen} bits by
contains a 20-bit value that will be converted into \Gls{xlen} bits by
using the {\em imm} operand for bits 31:12 and then sign-extending it
to the left\footnote{When XLEN is larger than 32.} and zero--extending
to the left\footnote{When XLEN is larger than 32.} and zero-extending
the LSBs as discussed in \autoref{extension:zr}.
If \Gls{xlen}=32 then the imm value in this example will be
@ -345,7 +345,7 @@ converted as shown below.
\DrawBitBoxSignLeftZeroRightExtendedPicture{32}{11010110000000000011}{12}
Notice that the 20--bits of the imm field are mapped in the same order and
Notice that the 20-bits of the imm field are mapped in the same order and
in the same relative position that they appear in the instruction when
they are used to create the value of the immediate operand.
Shifting the imm value to the left, into the ``upper bits'' of the immediate
@ -365,8 +365,8 @@ same two's complement integer value by extending the sign to the left.
\subsection{J Type}
\label{insnformat:jtype}
The J--type format is used for instructions that use a 20--bit immediate operand
and a destination register. It is similar to the U--type. However, the immediate
The J-type format is used for instructions that use a 20-bit immediate operand
and a destination register. It is similar to the U-type. However, the immediate
operand is constructed by arranging the {\em imm} bits in a different manner.
\DrawInsnTypeJTikz{00111001001110000001001111101111}
@ -375,16 +375,16 @@ The \reg{rd} field contains an \reg{x} register number to be set to a value that
depends on the instruction.
In the J--type format the 20 {\em imm} bits are arranged such
In the J-type format the 20 {\em imm} bits are arranged such
that they represent the ``lower'' portion of the immediate value. Unlike
the U--type
instructions, the J-type requires the bits to be re--ordered and shifted
to the right before they are used.\footnote{The reason that the J--type
the U-type
instructions, the J-type requires the bits to be re-ordered and shifted
to the right before they are used.\footnote{The reason that the J-type
bits are reordered like this is because it simplifies the implementation of
hardware as discussed in \autoref{section:EncodingFormats}.}
The example above shows that the bit positions in the {\em imm} field
description. We see that the 20 {\em imm} bits are re--ordered according to:
description. We see that the 20 {\em imm} bits are re-ordered according to:
[20\textbar10:1\textbar11\textbar19:12].
This means that the \acrshort{msb} of the {\em imm} field is to be placed
into bit 20 of the immediate integer value ultimately used by the instruction
@ -393,8 +393,8 @@ The next bit to the right in the {\em imm} field is to be placed into bit 10 of
the immediate value and so on.
After the {\em imm} bits are re-positioned into bits 20:1 of the immediate value
being constructed, a zero--bit will be added to the \acrshort{lsb}
and the value in bit--position 20 will be replicated to sign--extend the
being constructed, a zero-bit will be added to the \acrshort{lsb}
and the value in bit-position 20 will be replicated to sign-extend the
value to \Gls{xlen} bits as discussed in \autoref{extension:slzr}.
If \Gls{xlen}=32 then the {\em imm} value in this example will be converted as
@ -409,7 +409,7 @@ shown below.
%$0000000000000000000000000000000000000000000010000001101110010010_2$
%(\verb@0000000000081b92@$_16$).
A J--type example with a negative imm field:
A J-type example with a negative imm field:
\DrawInsnTypeJTikz{10111001001110000001001111101111}
@ -424,11 +424,11 @@ shown below.
%If \Gls{xlen}=32 then the imm value in this example will be converted to
%\verb@fffffffffff81b92@$_16$.
The J--type format is used by the Jump And Link instruction that calculates
The J-type format is used by the Jump And Link instruction that calculates
a target address by adding a signed immediate value to the current program
counter. Since no instruction can be placed at an odd address the 20--bit
imm value is zero--extended to the right to represent a 21-bit signed offset
capable of representing numbers twice the magnitude of the 20--bit imm value.
counter. Since no instruction can be placed at an odd address the 20-bit
imm value is zero-extended to the right to represent a 21-bit signed offset
capable of representing numbers twice the magnitude of the 20-bit imm value.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
@ -436,7 +436,7 @@ capable of representing numbers twice the magnitude of the 20--bit imm value.
\label{insnformat:rtype}
\DrawInsnTypeRTikz{01000001111100011000001110110011}
A special case of the R-type used for shift--immediate instructions where
A special case of the R-type used for shift-immediate instructions where
the {\em rs2} field is used as an immediate value named {\em shamt}
representing the number of bit positions to shift:
@ -537,11 +537,11 @@ x31 & t6 & Temporary & \\
Note that RISC-V is a little-endian machine.
All instructions must be naturally aligned to their 4--byte
All instructions must be naturally aligned to their 4-byte
boundaries.~\cite[p.~5]{rvismv1v22:2017}
If a RISC-V processor implements the C (compressed) extension then
instructions may be aligned to 2--byte
instructions may be aligned to 2-byte
boundaries.\cite[p.~68]{rvismv1v22:2017}
Data alignment is not necessary but unaligned data can be inefficient.
@ -571,7 +571,7 @@ Load Upper Immediate.
Copy the immediate value into bits 31:12 of the destination register and
place zeros into bits 11:0.
When XLEN is 64 or 128, the immediate value is sign--extended to the left.
When XLEN is 64 or 128, the immediate value is sign-extended to the left.
Instruction Format and Example:
@ -606,11 +606,11 @@ Add Upper Immediate to PC.
\verb@rd@ $\leftarrow$ \verb@pc + zr(imm)@
Create a signed 32--bit value by zero--extending imm[31:12] to the
Create a signed 32-bit value by zero-extending imm[31:12] to the
right (see \autoref{extension:zr}) and add this value to the
\reg{pc} register, placing the result into \reg{rd}.
When XLEN is 64 or 128, the immediate value is also sign--extended
When XLEN is 64 or 128, the immediate value is also sign-extended
to the left prior to being added to the \reg{pc} register.
\DrawInsnTypeUPicture{AUIPC t0, 3}{00000000000000000011001010110111}
@ -710,7 +710,7 @@ register and stores the sum into the \reg{pc} register causing
an unconditional branch to take place.
Note that the branch target address is calculated by
sign--extending the imm[11:0] bits from the instruction,
sign-extending the imm[11:0] bits from the instruction,
adding it to the \reg{rs1} register and {\em then} the
LSB of the sum is to zero and the result is stored into the
\reg{pc} register.
@ -877,7 +877,7 @@ Load byte.
\verb@pc@ $\leftarrow$ \verb@pc+4@
Load an 8-bit value from memory at address \verb@rs1+imm@, then
sign--extend it to 32 bits before storing it in \verb@rd@
sign-extend it to 32 bits before storing it in \verb@rd@
Encoding:
@ -894,7 +894,7 @@ Load halfword.
\verb@pc@ $\leftarrow$ \verb@pc+4@
Load a 16-bit value from memory at address \verb@rs1+imm@, then
sign--extend it to 32 bits before storing it in \verb@rd@
sign-extend it to 32 bits before storing it in \verb@rd@
Encoding:
@ -928,7 +928,7 @@ Load byte unsigned.
\verb@pc@ $\leftarrow$ \verb@pc+4@
Load an 8-bit value from memory at address \verb@rs1+imm@, then
zero--extend it to 32 bits before storing it in \verb@rd@
zero-extend it to 32 bits before storing it in \verb@rd@
Encoding:
@ -944,7 +944,7 @@ Load halfword unsigned.
\verb@pc@ $\leftarrow$ \verb@pc+4@
Load an 16-bit value from memory at address \verb@rs1+imm@, then
zero--extend it to 32 bits before storing it in \verb@rd@
zero-extend it to 32 bits before storing it in \verb@rd@
Encoding:
@ -1030,7 +1030,7 @@ Set LessThan Immediate
\verb@rd@ $\leftarrow$ \verb@(rs1 < sx(imm)) ? 1 : 0@\\
\verb@pc@ $\leftarrow$ \verb@pc+4@
If the sign--extended immediate value is less than the value
If the sign-extended immediate value is less than the value
in the \reg{rs1} register then the value 1 is stored in the
\reg{rd} register. Otherwise the value 0 is stored in the
\reg{rd} register.
@ -1056,7 +1056,7 @@ Set LessThan Immediate Unsigned
\verb@rd@ $\leftarrow$ \verb@(rs1 < sx(imm)) ? 1 : 0@\\
\verb@pc@ $\leftarrow$ \verb@pc+4@
If the sign--extended immediate value is less than the value
If the sign-extended immediate value is less than the value
in the \reg{rs1} register then the value 1 is stored in the
\reg{rd} register. Otherwise the value 0 is stored in the
\reg{rd} register. Both the immediate and \reg{rs1} register
@ -1086,7 +1086,7 @@ Exclusive Or Immediate
\verb@rd@ $\leftarrow$ \verb@rs1 ^ sx(imm)@\\
\verb@pc@ $\leftarrow$ \verb@pc+4@
The logical XOR of the sign--extended immediate value and the value
The logical XOR of the sign-extended immediate value and the value
in the \reg{rs1} register is stored in the \reg{rd} register.
Encoding:
@ -1110,7 +1110,7 @@ Or Immediate
\verb@rd@ $\leftarrow$ \verb@rs1 | sx(imm)@\\
\verb@pc@ $\leftarrow$ \verb@pc+4@
The logical OR of the sign--extended immediate value and the value
The logical OR of the sign-extended immediate value and the value
in the \reg{rs1} register is stored in the \reg{rd} register.
Encoding:
@ -1134,7 +1134,7 @@ And Immediate
\verb@rd@ $\leftarrow$ \verb@rs1 & sx(imm)@\\
\verb@pc@ $\leftarrow$ \verb@pc+4@
The logical AND of the sign--extended immediate value and the value
The logical AND of the sign-extended immediate value and the value
in the \reg{rs1} register is stored in the \reg{rd} register.
@ -1684,7 +1684,7 @@ read.~\cite[p.~22]{rvismv1v22:2017}
\subsection{MUL rd, rs1, rs2}
\index{Instruction!MUL}
Multiply \reg{rs1} by \reg{rs2} and store the least significant 32--bits
Multiply \reg{rs1} by \reg{rs2} and store the least significant 32-bits
of the result in \reg{rd}.
\DrawInsnTypeRPicture{MUL x7, x3, x31}{00000011111100111000001110110011}

2
book/toolchain/chapter.tex
View File

@ -70,7 +70,7 @@ text, data, bss, stack
Labels and scope.
Forward \& backward references to throw--away labels.
Forward \& backward references to throw-away labels.
The entry address of an application.