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Test factoring out the instruction details from the rv32 chapter.
This commit is contained in:
John Winans
parent
fe4b1434cf
commit
9aefc6131f
@ -299,15 +299,16 @@ to the left\footnote{When XLEN is larger than 32.} and zero-extending
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the LSBs as discussed in \autoref{extension:zr}.
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If \Gls{xlen}=32 then the {\em imm} value example will extracted from the instruction
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and converted as shown below.
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and converted as shown in \autoref{Figure:u_type_decode}.
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%\index{imm\_u}
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\label{imm.u:decode}\DrawInsnOpUTypeDecoding
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%If \Gls{xlen}=32 then the imm value in this example will be
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%converted as shown below.
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%
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%\DrawBitBoxSignLeftZeroRightExtendedPicture{32}{11010110000000000011}{12}
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\begin{figure}[ht]
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\centering
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\DrawInsnOpUTypeDecoding
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\captionof{figure}{Decoding a U-type instruction.}
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\label{Figure:u_type_decode}
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\label{imm.u:decode}
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\index{imm\protect\_u}
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\end{figure}
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Notice that the 20-bits of the imm field are mapped in the same order and
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in the same relative position that they appear in the instruction when
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@ -363,10 +364,17 @@ value to \Gls{xlen} bits as discussed in \autoref{extension:slzr}.
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If \Gls{xlen}=32 then the {\em imm} value example will extracted from the instruction
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and converted as shown below.
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and converted as shown in \autoref{Figure:j_type_decode}.
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\begin{figure}[ht]
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\centering
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\DrawInsnOpJTypeDecoding
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\captionof{figure}{Decoding a J-type instruction.}
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\label{Figure:j_type_decode}
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\label{imm.j:decode}
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\index{imm\protect\_j}
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\end{figure}
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%\index{imm\string_j}
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\label{imm.j:decode}\DrawInsnOpJTypeDecoding
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%\DrawBitBoxSignLeftZeroRightExtendedPicture{32}{01000000110111001001}{1}
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%
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@ -399,17 +407,30 @@ as well as to select between arithmetic and logical shifting.
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\DrawInsnTypeITikz{00000000010000011000001110000011}
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If \Gls{xlen}=32 then the {\em imm} value example will extracted from the instruction
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and converted as shown below.
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and converted as shown in \autoref{Figure:i_type_decode}.
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%\index{imm\_i}
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\label{imm.i:decode}\DrawInsnOpITypeDecoding
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\begin{figure}[ht]
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\centering
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\DrawInsnOpITypeDecoding
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\captionof{figure}{Decoding an I-type Instruction.}
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\label{Figure:i_type_decode}
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\label{imm.i:decode}
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\index{imm\protect\_i}
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\end{figure}
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A special case of the I-type used for shift-immediate instructions where
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the {\em imm} field is used as an immediate value named {\em shamt}
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representing the number of bit positions to shift:
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representing the number of bit positions to shift as shown in
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\autoref{Figure:shamt_i_type_decode}.
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%\index{shamt\_i}
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\label{shamt.i:decode}\DrawInsnOpIShiftTypeDecoding
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\begin{figure}[ht]
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\centering
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\DrawInsnOpIShiftTypeDecoding
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\captionof{figure}{Decoding an I-type Shift Instruction.}
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\label{Figure:shamt_i_type_decode}
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\label{shamt.i:decode}
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\index{shamt\protect\_i}
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\end{figure}
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Note that bit 30 is used to select between arithmetic and logical shifting.
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@ -421,10 +442,17 @@ Note that bit 30 is used to select between arithmetic and logical shifting.
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\DrawInsnTypeSTikz{00000000111100011000100110100011}
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If \Gls{xlen}=32 then the {\em imm} value example will extracted from the instruction
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and converted as shown below.
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and converted as shown \autoref{Figure:imm_s_type_decode}.
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\begin{figure}[ht]
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\centering
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\DrawInsnOpSTypeDecoding
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\captionof{figure}{Decoding an S-type Instruction.}
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\label{Figure:imm_s_type_decode}
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\label{imm.s:decode}
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\index{imm\protect\_s}
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\end{figure}
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%\index{imm\_s}
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\label{imm.s:decode}\DrawInsnOpSTypeDecoding
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{B Type}
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@ -432,17 +460,16 @@ and converted as shown below.
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\DrawInsnTypeBTikz{00000000111100011000100011100011}
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If \Gls{xlen}=32 then the {\em imm} value example will extracted from the instruction
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and converted as shown below.
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%\index{imm\_b}
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\label{imm.b:decode}\DrawInsnOpBTypeDecoding
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%insnTypeF
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%insnTypeCSRR
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and converted as shown in \autoref{Figure:imm_b_type_decode}.
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\begin{figure}[ht]
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\centering
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\DrawInsnOpBTypeDecoding
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\captionof{figure}{Decoding a B-type Instruction.}
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\label{Figure:imm_b_type_decode}
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\label{imm.b:decode}
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\index{imm\protect\_b}
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\end{figure}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{CPU Registers}
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@ -556,29 +583,31 @@ Copy the immediate value into bits 31:12 of the destination register and
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place zeros into bits 11:0.
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When XLEN is 64 or 128, the immediate value is sign-extended to the left.
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Instruction Format and Example:
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\input{insn/lui.tex}
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\DrawInsnTypeUPicture{LUI t0, 3}{00000000000000000011001010110111}
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\begin{verbatim}
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00010074: 000032b7 lui x5, 0x3 // x5 = 0x3000
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reg 0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 00003000 f0f0f0f0 f0f0f0f0
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reg 8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
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reg 16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
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reg 24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
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pc: 00010078
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\end{verbatim}
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\DrawInsnTypeUPicture{LUI t0, 0xfffff}{11111111111111111111001010110111}
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\begin{verbatim}
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00010078: fffff2b7 lui x5, 0xfffff // x5 = 0xfffff000
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reg 0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 fffff000 f0f0f0f0 f0f0f0f0
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reg 8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
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reg 16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
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reg 24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
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pc: 0001007c
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\end{verbatim}
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%Instruction Format and Example:
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%
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%\DrawInsnTypeUPicture{LUI t0, 3}{00000000000000000011001010110111}
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%
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%\begin{verbatim}
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%00010074: 000032b7 lui x5, 0x3 // x5 = 0x3000
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% reg 0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 00003000 f0f0f0f0 f0f0f0f0
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% reg 8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
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% reg 16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
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% reg 24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
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% pc: 00010078
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%\end{verbatim}
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%
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%\DrawInsnTypeUPicture{LUI t0, 0xfffff}{11111111111111111111001010110111}
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%
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%\begin{verbatim}
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%00010078: fffff2b7 lui x5, 0xfffff // x5 = 0xfffff000
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% reg 0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 fffff000 f0f0f0f0 f0f0f0f0
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% reg 8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
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% reg 16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
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% reg 24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
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% pc: 0001007c
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%\end{verbatim}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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@ -1520,181 +1549,4 @@ transferred back to a debugging environment.~\cite[p.~24]{rvismv1v22:2017}
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\DrawInsnTypeEPicture{EBREAK}{00000000000100000000000001110011}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{CSRRW rd, csr, rs1}
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\index{Instruction!CSRRW}
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The CSRRW (Atomic Read/Write CSR) instruction atomically swaps values in
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the CSRs and integer registers. CSRRW reads the old value of the CSR,
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zero-extends the value to XLEN bits, then writes it to integer register rd.
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The initial value in rs1 is written to the CSR. If rd=x0, then the
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instruction shall not read the CSR and shall not cause any of the
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side-effects that might occur on a CSR read.~\cite[p.~22]{rvismv1v22:2017}
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\DrawInsnTypeCSPicture{CSRRW x3, 2, x15}{00000000001001111001000111110011}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{CSRRS rd, csr, rs1}
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\index{Instruction!CSRRS}
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The CSRRS (Atomic Read and Set Bits in CSR) instruction reads the value
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of the CSR, zero-extends the value to XLEN bits, and writes it to integer
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register rd. The initial value in integer register rs1 is treated as a bit
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mask that specifies bit positions to be set in the CSR. Any bit that
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is high in rs1 will cause the corresponding bit to be set in the CSR,
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if that CSR bit is writable. Other bits in the CSR are unaffected (though
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CSRs might have side effects when written).~\cite[p.~22]{rvismv1v22:2017}
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If rs1=x0, then the instruction will not write
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to the CSR at all, and so shall not cause any of the side effects that
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might otherwise occur on a CSR write, such as raising illegal instruction
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exceptions on accesses to read-only CSRs. Note that if rs1 specifies a
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register holding a zero value other than x0, the instruction will still
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attempt to write the unmodified value back to the CSR and will cause any
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attendant side effects.~\cite[p.~22]{rvismv1v22:2017}
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\DrawInsnTypeCSPicture{CSRRS x3, 2, x15}{00000000001001111010000111110011}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{CSRRC rd, csr, rs1}
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\index{Instruction!CSRRC}
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The CSRRC (Atomic Read and Clear Bits in CSR) instruction reads the value
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of the CSR, zero-extends the value to XLEN bits, and writes it to integer
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register rd. The initial value in integer register rs1 is treated as a
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bit mask that specifies bit positions to be cleared in the CSR. Any bit
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that is high in rs1 will cause the corresponding bit to be cleared in
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the CSR, if that CSR bit is writable. Other bits in the CSR are
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unaffected.~\cite[p.~22]{rvismv1v22:2017}
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If rs1=x0, then the instruction will not write
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to the CSR at all, and so shall not cause any of the side effects that
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might otherwise occur on a CSR write, such as raising illegal instruction
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exceptions on accesses to read-only CSRs. Note that if rs1 specifies a
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register holding a zero value other than x0, the instruction will still
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attempt to write the unmodified value back to the CSR and will cause any
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attendant side effects.~\cite[p.~22]{rvismv1v22:2017}
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\DrawInsnTypeCSPicture{CSRRC x3, 2, x15}{00000000001001111011000111110011}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{CSRRWI rd, csr, imm}
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\index{Instruction!CSRRWI}
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This instruction is the same as CSRRW except a 5-bit unsigned (zero-extended)
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immediate value is used rather than the value from a register.
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\DrawInsnTypeCSIPicture{CSRRWI x3, 2, 7}{00000000001000111101000111110011}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{CSRRSI rd, csr, rs1}
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\index{Instruction!CSRRSI}
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This instruction is the same as CSRRS except a 5-bit unsigned (zero-extended)
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immediate value is used rather than the value from a register.
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If the uimm[4:0] field is zero, then this instruction will not
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write to the CSR, and shall not cause any of the side effects that
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might otherwise occur on a CSR write. For CSRRWI, if rd=x0, then
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the instruction shall not read the CSR and shall not cause any
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of the side-effects that might occur on a CSR
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read.~\cite[p.~22]{rvismv1v22:2017}
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\DrawInsnTypeCSIPicture{CSRRSI x3, 2, 7}{00000000001000111110000111110011}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{CSRRCI rd, csr, rs1}
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\index{Instruction!CSRRCI}
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This instruction is the same as CSRRC except a 5-bit unsigned (zero-extended)
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immediate value is used rather than the value from a register.
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If the uimm[4:0] field is zero, then this instruction will not
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write to the CSR, and shall not cause any of the side effects that
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might otherwise occur on a CSR write. For CSRRWI, if rd=x0, then
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the instruction shall not read the CSR and shall not cause any
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of the side-effects that might occur on a CSR
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read.~\cite[p.~22]{rvismv1v22:2017}
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\DrawInsnTypeCSIPicture{CSRRCI x3, 2, 7}{00000000001000111111000111110011}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\section{RV32M Standard Extension}
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\index{RV32M}
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32-bit integer multiply and divide instructions.
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{MUL rd, rs1, rs2}
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\index{Instruction!MUL}
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Multiply \reg{rs1} by \reg{rs2} and store the least significant 32-bits
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of the result in \reg{rd}.
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\DrawInsnTypeRPicture{MUL x7, x3, x31}{00000011111100111000001110110011}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{MULH rd, rs1, rs2}
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\index{Instruction!MULH}
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\DrawInsnTypeRPicture{MULH x7, x3, x31}{00000011111100111001001110110011}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{MULHS rd, rs1, rs2}
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\index{Instruction!MULHS}
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\DrawInsnTypeRPicture{MULHS x7, x3, x31}{00000011111100111010001110110011}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{MULHU rd, rs1, rs2}
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\index{Instruction!MULHU}
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\DrawInsnTypeRPicture{MULHU x7, x3, x31}{00000011111100111011001110110011}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{DIV rd, rs1, rs2}
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\index{Instruction!DIV}
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\DrawInsnTypeRPicture{DIV x7, x3, x31}{00000011111100111100001110110011}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{DIVU rd, rs1, rs2}
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\index{Instruction!DIVU}
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\DrawInsnTypeRPicture{DIVU x7, x3, x31}{00000011111100111101001110110011}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{REM rd, rs1, rs2}
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\index{Instruction!REM}
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\DrawInsnTypeRPicture{REM x7, x3, x31}{00000011111100111110001110110011}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{REMU rd, rs1, rs2}
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\index{Instruction!REMU}
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\DrawInsnTypeRPicture{REMU x7, x3, x31}{00000011111100111111001110110011}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\section{RV32A Standard Extension}
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\index{RV32A}
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32-bit atomic operations.
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\section{RV32F Standard Extension}
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\index{RV32F}
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32-bit IEEE floating point instructions.
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\section{RV32D Standard Extension}
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\index{RV32D}
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64-bit IEEE floating point instructions.
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21
book/rv32/insn/lui.tex
Normal file
21
book/rv32/insn/lui.tex
Normal file
@ -0,0 +1,21 @@
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\DrawInsnTypeUPicture{LUI t0, 3}{00000000000000000011001010110111}
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\begin{verbatim}
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00010074: 000032b7 lui x5, 0x3 // x5 = 0x3000
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reg 0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 00003000 f0f0f0f0 f0f0f0f0
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reg 8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
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reg 16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
|
||||
reg 24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
|
||||
pc: 00010078
|
||||
\end{verbatim}
|
||||
|
||||
\DrawInsnTypeUPicture{LUI t0, 0xfffff}{11111111111111111111001010110111}
|
||||
|
||||
\begin{verbatim}
|
||||
00010078: fffff2b7 lui x5, 0xfffff // x5 = 0xfffff000
|
||||
reg 0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 fffff000 f0f0f0f0 f0f0f0f0
|
||||
reg 8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
|
||||
reg 16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
|
||||
reg 24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
|
||||
pc: 0001007c
|
||||
\end{verbatim}
|
||||
Loading…
x
Reference in New Issue
Block a user