Test factoring out the instruction details from the rv32 chapter.

book/rv32/chapter.tex

@@ -299,15 +299,16 @@ to the left\footnote{When XLEN is larger than 32.} and zero-extending
 the LSBs as discussed in \autoref{extension:zr}.
 
 If \Gls{xlen}=32 then the {\em imm} value example will extracted from the instruction
-and converted as shown below.
+and converted as shown in \autoref{Figure:u_type_decode}.
 
-%\index{imm\_u}
+\begin{figure}[ht]
-\label{imm.u:decode}\DrawInsnOpUTypeDecoding
+\centering
-
+\DrawInsnOpUTypeDecoding
-%If \Gls{xlen}=32 then the imm value in this example will be
+\captionof{figure}{Decoding a U-type instruction.}
-%converted as shown below.
+\label{Figure:u_type_decode}
-%
+\label{imm.u:decode}
-%\DrawBitBoxSignLeftZeroRightExtendedPicture{32}{11010110000000000011}{12}
+\index{imm\protect\_u}
+\end{figure}
 
 Notice that the 20-bits of the imm field are mapped in the same order and 
 in the same relative position that they appear in the instruction when 
@@ -363,10 +364,17 @@ value to \Gls{xlen} bits as discussed in \autoref{extension:slzr}.
 
 
 If \Gls{xlen}=32 then the {\em imm} value example will extracted from the instruction
-and converted as shown below.
+and converted as shown in \autoref{Figure:j_type_decode}.
+
+\begin{figure}[ht]
+\centering
+\DrawInsnOpJTypeDecoding
+\captionof{figure}{Decoding a J-type instruction.}
+\label{Figure:j_type_decode}
+\label{imm.j:decode}
+\index{imm\protect\_j}
+\end{figure}
 
-%\index{imm\string_j}
-\label{imm.j:decode}\DrawInsnOpJTypeDecoding
 
 %\DrawBitBoxSignLeftZeroRightExtendedPicture{32}{01000000110111001001}{1}
 %
@@ -399,17 +407,30 @@ as well as to select between arithmetic and logical shifting.
 \DrawInsnTypeITikz{00000000010000011000001110000011}
 
 If \Gls{xlen}=32 then the {\em imm} value example will extracted from the instruction
-and converted as shown below.
+and converted as shown in \autoref{Figure:i_type_decode}.
 
-%\index{imm\_i}
+\begin{figure}[ht]
-\label{imm.i:decode}\DrawInsnOpITypeDecoding
+\centering
+\DrawInsnOpITypeDecoding
+\captionof{figure}{Decoding an I-type Instruction.}
+\label{Figure:i_type_decode}
+\label{imm.i:decode}
+\index{imm\protect\_i}
+\end{figure}
 
 A special case of the I-type used for shift-immediate instructions where 
 the {\em imm} field is used as an immediate value named {\em shamt} 
-representing the number of bit positions to shift:
+representing the number of bit positions to shift as shown in 
+\autoref{Figure:shamt_i_type_decode}.
 
-%\index{shamt\_i}
+\begin{figure}[ht]
-\label{shamt.i:decode}\DrawInsnOpIShiftTypeDecoding
+\centering
+\DrawInsnOpIShiftTypeDecoding
+\captionof{figure}{Decoding an I-type Shift Instruction.}
+\label{Figure:shamt_i_type_decode}
+\label{shamt.i:decode}
+\index{shamt\protect\_i}
+\end{figure}
 
 Note that bit 30 is used to select between arithmetic and logical shifting.
 
@@ -421,10 +442,17 @@ Note that bit 30 is used to select between arithmetic and logical shifting.
 \DrawInsnTypeSTikz{00000000111100011000100110100011}
 
 If \Gls{xlen}=32 then the {\em imm} value example will extracted from the instruction
-and converted as shown below.
+and converted as shown \autoref{Figure:imm_s_type_decode}.
+
+\begin{figure}[ht]
+\centering
+\DrawInsnOpSTypeDecoding
+\captionof{figure}{Decoding an S-type Instruction.}
+\label{Figure:imm_s_type_decode}
+\label{imm.s:decode}
+\index{imm\protect\_s}
+\end{figure}
 
-%\index{imm\_s}
-\label{imm.s:decode}\DrawInsnOpSTypeDecoding
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 \subsection{B Type}
@@ -432,17 +460,16 @@ and converted as shown below.
 \DrawInsnTypeBTikz{00000000111100011000100011100011}
 
 If \Gls{xlen}=32 then the {\em imm} value example will extracted from the instruction
-and converted as shown below.
+and converted as shown in \autoref{Figure:imm_b_type_decode}.
-
-%\index{imm\_b}
-\label{imm.b:decode}\DrawInsnOpBTypeDecoding
-
-
-%insnTypeF
-%insnTypeCSRR
-
-
 
+\begin{figure}[ht]
+\centering
+\DrawInsnOpBTypeDecoding
+\captionof{figure}{Decoding a B-type Instruction.}
+\label{Figure:imm_b_type_decode}
+\label{imm.b:decode}
+\index{imm\protect\_b}
+\end{figure}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 \subsection{CPU Registers}
@@ -556,29 +583,31 @@ Copy the immediate value into bits 31:12 of the destination register and
 place zeros into bits 11:0.
 When XLEN is 64 or 128, the immediate value is sign-extended to the left.
 
-Instruction Format and Example:
+\input{insn/lui.tex}
 
-\DrawInsnTypeUPicture{LUI t0, 3}{00000000000000000011001010110111}
+%Instruction Format and Example:
-
+%
-\begin{verbatim}
+%\DrawInsnTypeUPicture{LUI t0, 3}{00000000000000000011001010110111}
-00010074: 000032b7  lui     x5, 0x3         // x5 = 0x3000
+%
- reg  0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 00003000 f0f0f0f0 f0f0f0f0
+%\begin{verbatim}
- reg  8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
+%00010074: 000032b7  lui     x5, 0x3         // x5 = 0x3000
- reg 16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
+% reg  0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 00003000 f0f0f0f0 f0f0f0f0
- reg 24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
+% reg  8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
-     pc: 00010078
+% reg 16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
-\end{verbatim}
+% reg 24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
-
+%     pc: 00010078
-\DrawInsnTypeUPicture{LUI t0, 0xfffff}{11111111111111111111001010110111}
+%\end{verbatim}
-
+%
-\begin{verbatim}
+%\DrawInsnTypeUPicture{LUI t0, 0xfffff}{11111111111111111111001010110111}
-00010078: fffff2b7  lui     x5, 0xfffff         // x5 = 0xfffff000
+%
- reg  0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 fffff000 f0f0f0f0 f0f0f0f0
+%\begin{verbatim}
- reg  8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
+%00010078: fffff2b7  lui     x5, 0xfffff         // x5 = 0xfffff000
- reg 16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
+% reg  0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 fffff000 f0f0f0f0 f0f0f0f0
- reg 24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
+% reg  8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
-     pc: 0001007c
+% reg 16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
-\end{verbatim}
+% reg 24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
+%     pc: 0001007c
+%\end{verbatim}
 
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
@@ -1520,181 +1549,4 @@ transferred back to a debugging environment.~\cite[p.~24]{rvismv1v22:2017}
 
 \DrawInsnTypeEPicture{EBREAK}{00000000000100000000000001110011}
 
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{CSRRW rd, csr, rs1}
-\index{Instruction!CSRRW}
 
-The CSRRW (Atomic Read/Write CSR) instruction atomically swaps values in 
-the CSRs and integer registers. CSRRW reads the old value of the CSR, 
-zero-extends the value to XLEN bits, then writes it to integer register rd. 
-The initial value in rs1 is written to the CSR. If rd=x0, then the 
-instruction shall not read the CSR and shall not cause any of the 
-side-effects that might occur on a CSR read.~\cite[p.~22]{rvismv1v22:2017}
-
-\DrawInsnTypeCSPicture{CSRRW x3, 2, x15}{00000000001001111001000111110011}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{CSRRS rd, csr, rs1}
-\index{Instruction!CSRRS}
-
-The CSRRS (Atomic Read and Set Bits in CSR) instruction reads the value 
-of the CSR, zero-extends the value to XLEN bits, and writes it to integer 
-register rd. The initial value in integer register rs1 is treated as a bit 
-mask that specifies bit positions to be set in the CSR. Any bit that
-is high in rs1 will cause the corresponding bit to be set in the CSR, 
-if that CSR bit is writable.  Other bits in the CSR are unaffected (though 
-CSRs might have side effects when written).~\cite[p.~22]{rvismv1v22:2017}
-
-If rs1=x0, then the instruction will not write 
-to the CSR at all, and so shall not cause any of the side effects that 
-might otherwise occur on a CSR write, such as raising illegal instruction 
-exceptions on accesses to read-only CSRs. Note that if rs1 specifies a 
-register holding a zero value other than x0, the instruction will still 
-attempt to write the unmodified value back to the CSR and will cause any 
-attendant side effects.~\cite[p.~22]{rvismv1v22:2017}
-
-\DrawInsnTypeCSPicture{CSRRS x3, 2, x15}{00000000001001111010000111110011}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{CSRRC rd, csr, rs1}
-\index{Instruction!CSRRC}
-
-The CSRRC (Atomic Read and Clear Bits in CSR) instruction reads the value 
-of the CSR, zero-extends the value to XLEN bits, and writes it to integer 
-register rd. The initial value in integer register rs1 is treated as a 
-bit mask that specifies bit positions to be cleared in the CSR. Any bit
-that is high in rs1 will cause the corresponding bit to be cleared in 
-the CSR, if that CSR bit is writable. Other bits in the CSR are 
-unaffected.~\cite[p.~22]{rvismv1v22:2017}
-
-If rs1=x0, then the instruction will not write 
-to the CSR at all, and so shall not cause any of the side effects that 
-might otherwise occur on a CSR write, such as raising illegal instruction 
-exceptions on accesses to read-only CSRs. Note that if rs1 specifies a 
-register holding a zero value other than x0, the instruction will still 
-attempt to write the unmodified value back to the CSR and will cause any 
-attendant side effects.~\cite[p.~22]{rvismv1v22:2017}
-
-\DrawInsnTypeCSPicture{CSRRC x3, 2, x15}{00000000001001111011000111110011}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{CSRRWI rd, csr, imm}
-\index{Instruction!CSRRWI}
-
-This instruction is the same as CSRRW except a 5-bit unsigned (zero-extended)
-immediate value is used rather than the value from a register.
-
-\DrawInsnTypeCSIPicture{CSRRWI x3, 2, 7}{00000000001000111101000111110011}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{CSRRSI rd, csr, rs1}
-\index{Instruction!CSRRSI}
-
-This instruction is the same as CSRRS except a 5-bit unsigned (zero-extended)
-immediate value is used rather than the value from a register.
-
-If the uimm[4:0] field is zero, then this instruction will not
-write to the CSR, and shall not cause any of the side effects that 
-might otherwise occur on a CSR write. For CSRRWI, if rd=x0, then 
-the instruction shall not read the CSR and shall not cause any
-of the side-effects that might occur on a CSR 
-read.~\cite[p.~22]{rvismv1v22:2017}
-
-\DrawInsnTypeCSIPicture{CSRRSI x3, 2, 7}{00000000001000111110000111110011}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{CSRRCI rd, csr, rs1}
-\index{Instruction!CSRRCI}
-
-This instruction is the same as CSRRC except a 5-bit unsigned (zero-extended)
-immediate value is used rather than the value from a register.
-
-If the uimm[4:0] field is zero, then this instruction will not
-write to the CSR, and shall not cause any of the side effects that 
-might otherwise occur on a CSR write. For CSRRWI, if rd=x0, then 
-the instruction shall not read the CSR and shall not cause any
-of the side-effects that might occur on a CSR 
-read.~\cite[p.~22]{rvismv1v22:2017}
-
-\DrawInsnTypeCSIPicture{CSRRCI x3, 2, 7}{00000000001000111111000111110011}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\section{RV32M Standard Extension}
-\index{RV32M}
-
-32-bit integer multiply and divide instructions.
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{MUL rd, rs1, rs2}
-\index{Instruction!MUL}
-
-Multiply \reg{rs1} by \reg{rs2} and store the least significant 32-bits
-of the result in \reg{rd}.
-
-\DrawInsnTypeRPicture{MUL x7, x3, x31}{00000011111100111000001110110011}
-
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{MULH rd, rs1, rs2}
-\index{Instruction!MULH}
-
-\DrawInsnTypeRPicture{MULH x7, x3, x31}{00000011111100111001001110110011}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{MULHS rd, rs1, rs2}
-\index{Instruction!MULHS}
-
-\DrawInsnTypeRPicture{MULHS x7, x3, x31}{00000011111100111010001110110011}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{MULHU rd, rs1, rs2}
-\index{Instruction!MULHU}
-
-\DrawInsnTypeRPicture{MULHU x7, x3, x31}{00000011111100111011001110110011}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{DIV rd, rs1, rs2}
-\index{Instruction!DIV}
-
-\DrawInsnTypeRPicture{DIV x7, x3, x31}{00000011111100111100001110110011}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{DIVU rd, rs1, rs2}
-\index{Instruction!DIVU}
-
-\DrawInsnTypeRPicture{DIVU x7, x3, x31}{00000011111100111101001110110011}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{REM rd, rs1, rs2}
-\index{Instruction!REM}
-
-\DrawInsnTypeRPicture{REM x7, x3, x31}{00000011111100111110001110110011}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{REMU rd, rs1, rs2}
-\index{Instruction!REMU}
-
-\DrawInsnTypeRPicture{REMU x7, x3, x31}{00000011111100111111001110110011}
-
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\section{RV32A Standard Extension}
-\index{RV32A}
-
-32-bit atomic operations.
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\section{RV32F Standard Extension}
-\index{RV32F}
-
-32-bit IEEE floating point instructions.
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\section{RV32D Standard Extension}
-\index{RV32D}
-
-64-bit IEEE floating point instructions.

book/rv32/insn/lui.tex

@@ -0,0 +1,21 @@
+\DrawInsnTypeUPicture{LUI t0, 3}{00000000000000000011001010110111}
+
+\begin{verbatim}
+00010074: 000032b7  lui     x5, 0x3         // x5 = 0x3000
+ reg  0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 00003000 f0f0f0f0 f0f0f0f0
+ reg  8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
+ reg 16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
+ reg 24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
+     pc: 00010078
+\end{verbatim}
+
+\DrawInsnTypeUPicture{LUI t0, 0xfffff}{11111111111111111111001010110111}
+
+\begin{verbatim}
+00010078: fffff2b7  lui     x5, 0xfffff         // x5 = 0xfffff000
+ reg  0: 00000000 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 fffff000 f0f0f0f0 f0f0f0f0
+ reg  8: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
+ reg 16: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
+ reg 24: f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0-f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0
+     pc: 0001007c
+\end{verbatim}