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Improve clarity of the LI and LA pseudo instructions
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John Winans
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@ -364,26 +364,27 @@ Introduce and present subroutines but not nesting until introduce stack operatio
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{\small
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\begin{verbatim}
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li rd,constant lui rd,(constant >>U 12)+(constant & 0x00000800 ? 1 : 0)
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li rd,constant
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lui rd,(constant + 0x00000800) >> 12
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addi rd,rd,(constant & 0x00000fff)
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la rd,label
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auipc rd,((label-.) >>U 12) + ((label-.) & 0x00000800 ? 1 : 0)
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auipc rd,((label-.) + 0x00000800) >> 12
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addi rd,rd,((label-(.-4)) & 0x00000fff)
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l{b|h|w} rd,label
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auipc rd,((label-.) >>U 12) + ((label-.) & 0x00000800 ? 1 : 0)
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auipc rd,((label-.) + 0x00000800) >> 12
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l{b|h|w} rd,((label-(.-4)) & 0x00000fff)(rd)
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s{b|h|w} rd,label,rt # rt used as a temp reg for the operation (default=x6)
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auipc rt,((label-.) >>U 12) + ((label-.) & 0x00000800 ? 1 : 0)
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auipc rt,((label-.) + 0x00000800) >> 12
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s{b|h|w} rd,((label-(.-4)) & 0x00000fff)(rt)
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call label auipc x1,((label-.) >>U 12) + ((label-.) & 0x00000800 ? 1 : 0)
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call label auipc x1,((label-.) + 0x00000800) >> 12
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jalr x1,((label-(.-4)) & 0x00000fff)(x1)
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tail label,rt # rt used as a temp reg for the operation (default=x6)
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auipc rt,((label-.) >>U 12) + ((label-.) & 0x00000800 ? 1 : 0)
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auipc rt,((label-.) + 0x00000800) >> 12
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jalr x0,((label-(.-4)) & 0x00000fff)(rt)
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mv rd,rs addi rd,rs,0
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@ -398,7 +399,8 @@ Introduce and present subroutines but not nesting until introduce stack operatio
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\subsection{The {\tt li} Pseudoinstruction}
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Note that the {\tt li} pseudoinstruction includes a conditional addition of 1 to the operand
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Note that the {\tt li} pseudoinstruction includes an (effectively) conditional addition
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of 1 to the immediate operand
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in the {\tt lui} instruction. This is because the immediate operand in the
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{\tt addi} instruction is sign-extended before it is added to \verb@rd@.
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If the immediate operand to the {\tt addi} has its most-significant-bit set to 1 then
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@ -422,32 +424,56 @@ A naive (incorrect) solution might be:
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The result of the above code is that an incorrect value has been placed into x5.
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}
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To remedy this problem, the value used in the {\tt lui} instruction can altered
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To remedy this problem, the value used in the {\tt lui} instruction can be altered
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(by adding 1 to its operand) to compensate for the sign-extention in the {\tt addi}
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instruction:
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{\small
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\begin{verbatim}
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lui x5,0x12346 // x5 = 0x12346000 (note: this is 0x12345000 + 0x1000)
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lui x5,0x12346 // x5 = 0x12346000 (note: this is 0x12345800 + 0x0800)
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addi x5,x5,0x800 // x5 = 0x12346000 + sx(0x800) = 0x12346000 + 0xfffff800 = 0x12345800
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\end{verbatim}
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}
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Keep in mind that the {\em only} time that this altering of the operand in the {\tt lui}
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instruction should take place is when the most-significant-bit of the operand in the
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{\tt addi} is set to one.
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Keep in mind that the {\tt li} pseudoinstruction must {\em only} increment the operand
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of the {\tt lui} instruction when it is known that the operand of the subsequent
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{\tt addi} instruction will be a negative number.
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\enote{Add a ribbon diagram of this?}%
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By adding {\tt 0x00000800} to the immediate operand of the {\tt lui} instruction in
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this example, a carry-bit into bit-12 will be set to {\tt 1} iff the value in
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bits 11-0 will be treated as a negative value in the subsequent {\tt addi} instruction.
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In other words, when bit-11 is set to {\tt 1} in the immediate operand of the {\tt li}
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pseudoinstruction, the immediate operand of the {\tt lui} instruction will be
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incremented by {\tt 1}.
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Consider the case where we wish to put the value {\tt 0x12345700} into register {\tt x5}:
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{\small
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\begin{verbatim}
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lui x5,0x12345 // x5 = 0x12345000 (note this is 0x12345 + 0)
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lui x5,0x12345 // x5 = 0x12345000 (note that 0x12345700 + 0x0800 = 0x12345f00)
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addi x5,x5,0x700 // x5 = 0x12345000 + sx(0x700) = 0x12345000 + 0x00000700 = 0x12345700
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\end{verbatim}
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}
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The sign-extension in this example performed by the {\tt addi} instruction will convert the
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{\tt 0x700} to {\tt 0x00000700} before the addition.
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Therefore, the {\tt li} pseudoinstruction must {\em only} increment the operand of the
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{\tt lui} instruction when it is known that the operand of the subsequent {\tt addi}
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instruction will be a negative number.
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Observe that {\tt 0x12345700+0x0800 = 0x12345f00} and therefore, after shifting
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to the right, the least significant {\tt 0xf00} is truncated, leaving {\tt 0x12345} as
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the immediate operand of the {\tt lui} instruction. The addition of
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{\tt 0x0800} in this example has no effect on the immediate operand of the {\tt lui}
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instruction because bit-11 in the original value {\tt 0x12345700} is zero.
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A general algorithm for implementing the {\tt li rd,constant} pseudoinstruction is:
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{\small
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\begin{verbatim}
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lui rd,(constant + 0x00000800) >> 12
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addi rd,rd,(constant & 0x00000fff) // the 12-bit immediate is sign extended
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\end{verbatim}
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}
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\enote{Find a proper citation for this.}%
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Note that on RV64 and RV128 systems, the {\tt lui} places the immediate operand into
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bits 31-12 and then sign-extends the result to {\tt XLEN} bits.
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@ -477,10 +503,10 @@ into register x10:
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00010900 .word 999 # a 32-bit integer constant stored in memory at address var1
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\end{verbatim}
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}
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The \verb@la@ instruction here will expand into:
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The \verb@la@ instruction in this example will expand into:
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{\small
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\begin{verbatim}
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00010040 auipc x10,((var1-.) >>U 12) + ((var1-.) & 0x00000800 ? 1 : 0)
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00010040 auipc x10,((var1-.) + 0x00000800) >> 12
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00010044 addi x10,x10,((var1-(.-4)) & 0x00000fff)
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\end{verbatim}
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}
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@ -494,43 +520,39 @@ represented by the label \verb@var1@ from the address of the current instruction
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to the target label\ldots{} which is \verb@0x000008c0@.
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Therefore the expanded pseudoinstruction example will become:
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{\small
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\begin{verbatim}
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00010040 auipc x10,((0x00010900-0x00010040) >>U 12) + ((0x00010900-0x00010040) & 0x00000800 ? 1 : 0)
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00010044 addi x10,x10,((0x00010900-(0x00010044-4)) & 0x00000fff) # note the extra -4 here!
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00010040 auipc x10,((0x00010900 - 0x00010040) + 0x00000800) >> 12
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00010044 addi x10,x10,((0x00010900 - (0x00010044 - 4)) & 0x00000fff) # note the extra -4 here!
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\end{verbatim}
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}
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After performing the subtractions, it will reduce to this:
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{\small
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\begin{verbatim}
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00010040 auipc x10,(0x000008c0 >>U 12) + ((0x000008c0) & 0x00000800 ? 1 : 0)
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00010040 auipc x10,(0x000008c0 + 0x00000800) >> 12
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00010044 addi x10,x10,(0x000008c0 & 0x00000fff)
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\end{verbatim}
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}
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Continuing to reduce the math operations we get:
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{\small
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\begin{verbatim}
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00010040 auipc x10,0x00000 + 1 # add 1 here because 0x8c0 below has MSB = 1
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00010040 auipc x10,0x00001 # 0x000008c0 + 0x00000800 = 0x000010c0
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00010044 addi x10,x10,0x8c0
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\end{verbatim}
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}
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\ldots and\ldots
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{\small
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\begin{verbatim}
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00010040 auipc x10,0x00001
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00010044 addi x10,x10,0x8c0
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\end{verbatim}
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}
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Note that the the \verb@la@ exhibits the same sort of technique as the \verb@li@ in that
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Note that the \verb@la@ pseudoinstruction exhibits the same sort of technique as
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the \verb@li@ in that
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if/when the immediate operand of the \verb@addi@ instruction has its most significant
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bit set then the operand in the \verb@auipc@ has to be incremented by 1 to compensate.
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\section{Relocation}
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Because expressions that refer to constants and address labels are common in
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@ -545,12 +567,12 @@ that appears in instructions like \verb@addi@ and \verb@jalr@.)
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To refer to an absolute value, the following operators can be used:
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{\small
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\begin{verbatim}
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%hi(constant) // becomes: (constant >>U 12)+(constant & 0x00000800 ? 1 : 0)
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%hi(constant) // becomes: (constant + 0x00000800) >> 12
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%lo(constant) // becomes: (constant & 0x00000fff)
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\end{verbatim}
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}
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Thus, the \verb@li@ pseudoinstruction can be expressed like this:
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Thus, the \verb@li@ pseudoinstruction can, therefore, be expressed like this:
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{\small
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\begin{verbatim}
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@ -566,7 +588,7 @@ Thus, the \verb@li@ pseudoinstruction can be expressed like this:
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The following can be used for PC-relative addresses:
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{\small
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\begin{verbatim}
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%pcrel_hi(symbol) // becomes: ((symbol-.) >>U 12) + ((symbol-.) & 0x00000800 ? 1 : 0)
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%pcrel_hi(symbol) // becomes: ((symbol-.) + 0x0800) >> 12
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%pcrel_lo(lab) // becomes: ((symbol-lab) & 0x00000fff)
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\end{verbatim}
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}
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@ -589,7 +611,7 @@ Examples of using the \verb@auipc@ \& \verb@addi@ together with \verb@%pcrel_hi(
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{\small
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\begin{verbatim}
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xxx: auipc t1,%pcrel_hi(yyy) // (yyy-.) >>U 12) + ((yyy-.) & 0x00000800 ? 1 : 0)
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xxx: auipc t1,%pcrel_hi(yyy) // ((yyy-.) + 0x0800) >> 12
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addi t1,t1,%pcrel_lo(xxx) // ((yyy-xxx) & 0x00000fff)
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...
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yyy: // the address: yyy is saved into t1 above
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@ -610,9 +632,13 @@ label: auipc t1,%pcrel_hi(symbol)
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\end{verbatim}
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}
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\section{Relaxation}
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\enote{I'm not sure I want to get into the details of how this is done. Just assume it works.}%
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%\enote{I'm not sure I want to get into the details of how this is done. Just assume it works.}%
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In the simplest of terms, {\em Relaxation} refers to the ability of the
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linker (not the compiler!) to determine if/when the instructions that
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were generated with the \verb@xxx_hi@ and \verb@xxx_lo@ operators are
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