mirror of
https://github.com/johnwinans/rvalp.git
synced 2025-09-27 13:12:03 -04:00
Add an insn summary and reference card
This commit is contained in:
John Winans
parent
33cb8fe72d
commit
e5b7740d5f
@ -2,6 +2,7 @@
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%\documentclass[letterpaper]{book}
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\documentclass[oneside,letterpaper]{book}
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\input{preamble}
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\input{colors}
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\input{insnformats}
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@ -22,10 +23,11 @@
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\makenoidxglossaries
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\include{glossary}
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%\includeonly{refcard/chapter}
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\begin{document}
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\include{indexrefs} % The see-references for the index
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% Why does this (apparently) have to go here????
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\newlength{\fullwidth}
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\setlength{\fullwidth}{\the\textwidth}
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@ -68,6 +70,7 @@
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% These 'chapters' are lettered rather than numbered
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\appendix
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\include{insnsummary/chapter}
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\include{install/chapter}
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\include{toolchain/chapter}
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\include{float/chapter}
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@ -78,25 +81,22 @@
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\backmatter
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% putting a chapter here causes it to be unnumbered
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%\clearpage
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\bibliography{bibliography}
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\addcontentsline{toc}{chapter}{Bibliography}
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\nocite{*} % force all bib items to file appear even if not cited
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%\bibliographystyle{alpha}
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\bibliographystyle{ieeetr}
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%\clearpage
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%\phantomsection
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\glsaddall
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\printnoidxglossaries
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%\printglossary
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%\clearpage
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\phantomsection
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\addcontentsline{toc}{chapter}{\indexname}
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\printindex
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\include{refcard/chapter}
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\end{document}
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@ -534,6 +534,57 @@
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\newcommand\xTInsnStatement[4]{%
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\parbox{3.5cm}{{\sffamily\large\bfseries #2}\\
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\tt#3}\hspace{5mm}\parbox{5cm}{\bfseries#1}\parbox{12cm}{#4}%
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}
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\newcommand\TInsnStatement[4]{%
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\begin{tabular}{lll}
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\parbox[t]{3.5cm}{{\sffamily\large\bfseries #2}\\
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\tt#3} & \parbox[t]{5cm}{\bfseries #1} & \parbox[t]{12cm}{#4}\\
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\end{tabular}
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}
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\newcommand\TDrawInsnTypeUPicture[5]{%
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\TInsnStatement{#1}{#2}{#3}{#4}\\
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\DrawInsnTypeUTikz{#5}%
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}
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\newcommand\TDrawInsnTypeJPicture[5]{%
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\TInsnStatement{#1}{#2}{#3}{#4}\\
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\DrawInsnTypeJTikz{#5}%
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}
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\newcommand\TDrawInsnTypeBPicture[5]{%
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\TInsnStatement{#1}{#2}{#3}{#4}\\
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\DrawInsnTypeBTikz{#5}%
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}
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\newcommand\TDrawInsnTypeIPicture[5]{%
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\TInsnStatement{#1}{#2}{#3}{#4}\\
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\DrawInsnTypeITikz{#5}%
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}
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\newcommand\TDrawInsnTypeSPicture[5]{%
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\TInsnStatement{#1}{#2}{#3}{#4}\\
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\DrawInsnTypeSTikz{#5}%
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}
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\newcommand\TDrawInsnTypeRPicture[5]{%
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\TInsnStatement{#1}{#2}{#3}{#4}\\
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\DrawInsnTypeRTikz{#5}%
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}
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\newcommand\TDrawInsnTypeRShiftPicture[5]{
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\TInsnStatement{#1}{#2}{#3}{#4}\\
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\DrawInsnTypeRShiftTikz{#5}
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}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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346
book/insnsummary/chapter.tex
Normal file
346
book/insnsummary/chapter.tex
Normal file
@ -0,0 +1,346 @@
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\chapter{Instruction Set Summary}
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\enote{Once the RV32I section is re-factored, it may end up turning into this.}
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\TDrawInsnTypeUPicture
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{Load Upper Immediate}
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{lui rd, imm}
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{lui t0, 3}
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{\tt%
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rd $\leftarrow$ pc + sx(imm<<1)\\
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pc $\leftarrow$ pc + 4}
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{00000000000000000011001010110111}
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\TDrawInsnTypeUPicture
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{Add Upper Immediate PC}
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{auipc rd, imm}
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{auipc t0, 3}
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{\tt%
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rd $\leftarrow$ pc + zr(imm)\\
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pc $\leftarrow$ pc + 4}
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{000000000000000000110010101xxxxx}
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\TDrawInsnTypeJPicture
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{Jump And Link}
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{jal rd, imm}
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{jal x7, .+16}
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{\tt%
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rd $\leftarrow$ pc + 4\\
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pc $\leftarrow$ pc + sx(imm<<1)}
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{00000001000000000000001111101111}
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\TDrawInsnTypeIPicture
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{Jump And Link Register}
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{jalr rd, rs1, imm}
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{jalr x1, x7, 4}
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{\tt%
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rd $\leftarrow$ pc + 4\\
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pc $\leftarrow$ (rs1 + sx(imm)) \& \textasciitilde{}1}
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{00000000010000111000000011100111}
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\enote{These branches (and likely other insns) are not encoded properly!}
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\TDrawInsnTypeBPicture
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{Branch Equal}
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{beq rs1, rs2, imm}
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{beq x3, x15, 2064}
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{\tt pc $\leftarrow$ (rs1==rs2) ? pc+sx(imm[12:1]<<1) : pc+4}
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{00000000111100011000100011100011}
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\TDrawInsnTypeBPicture
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{Branch Not Equal}
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{bne rs1, rs2, imm}
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{bne x3, x15, 2064}
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{\tt pc $\leftarrow$ (rs1!=rs2) ? pc+sx(imm[12:1]<<1) : pc+4}
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{00000000111100011001100011100011}
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\TDrawInsnTypeBPicture
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{Branch Less Than}
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{blt rs1, rs2, imm}
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{blt x3, x15, 2064}
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{\tt pc $\leftarrow$ (rs1<rs2) ? pc+sx(imm[12:1]<<1) : pc+4}
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{00000000111100011100100011100011}
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\TDrawInsnTypeBPicture
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{Branch Greater or Equal}
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{bge rs1, rs2, imm}
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{bge x3, x15, 2064}
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{\tt pc $\leftarrow$ (rs1>=rs2) ? pc+sx(imm[12:1]<<1) : pc+4}
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{00000000111100011101100011100011}
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\TDrawInsnTypeBPicture
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{Branch Less Than Unsigned}
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{bltu rs1, rs2, imm}
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{bltu x3, x15, 2064}
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{\tt pc $\leftarrow$ (rs1<rs2) ? pc+sx(imm[12:1]<<1) : pc+4}
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{00000000111100011110100011100011}
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\TDrawInsnTypeBPicture
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{Branch Greater or Equal Unsigned}
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{bgeu rs1, rs2, imm}
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{bgeu x3, x15, 2064}
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{\tt pc $\leftarrow$ (rs1>=rs2) ? pc+sx(imm[12:1]<<1) : pc+4}
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{00000000111100011111100011100011}
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\TDrawInsnTypeIPicture
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{Load Byte}
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{lb rd, imm(rs1)}
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{lb x7, 4(x3)}
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{\tt%
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rd $\leftarrow$ sx(m8(rs1+sx(imm)))\\
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pc $\leftarrow$ pc+4}
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{00000000010000011000001110000011}
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\TDrawInsnTypeIPicture
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{Load Halfword}
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{lh rd, imm(rs1)}
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{lh x7, 4(x3)}
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{\tt%
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rd $\leftarrow$ sx(m16(rs1+sx(imm)))\\
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pc $\leftarrow$ pc+4}
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{00000000010000011001001110000011}
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\TDrawInsnTypeIPicture
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{Load Word}
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{lw rd, imm(rs1)}
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{lw x7, 4(x3)}
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{\tt%
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rd $\leftarrow$ sx(m32(rs1+sx(imm)))\\
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pc $\leftarrow$ pc+4}
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{00000000010000011010001110000011}
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\TDrawInsnTypeIPicture
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{Load Byte Unsigned}
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{lbu rd, imm(rs1)}
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{lbu x7, 4(x3)}
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{\tt%
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rd $\leftarrow$ zx(m8(rs1+sx(imm)))\\
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pc $\leftarrow$ pc+4}
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{00000000010000011100001110000011}
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\TDrawInsnTypeIPicture
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{Load Halfword Unsigned}
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{lhu rd, imm(rs1)}
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{lhu x7, 4(x3)}
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{\tt%
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rd $\leftarrow$ zx(m16(rs1+sx(imm)))\\
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pc $\leftarrow$ pc+4}
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{00000000010000011101001110000011}
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\TDrawInsnTypeSPicture
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{Store Byte}
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{sb rs2, imm(rs1)}
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{sb x3, 19(x15)}
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{\tt%
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m8(rs1+sx(imm)) $\leftarrow$ rs2[7:0]\\
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pc $\leftarrow$ pc+4}
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{00000000111100011000100110100011}
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\TDrawInsnTypeSPicture
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{Store Halfword}
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{sh rs2, imm(rs1)}
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{sh x3, 19(x15)}
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{\tt%
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m16(rs1+sx(imm)) $\leftarrow$ rs2[15:0]\\
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pc $\leftarrow$ pc+4}
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{00000000111100011001100110100011}
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\TDrawInsnTypeSPicture
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{Store Word}
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{sw rs2, imm(rs1)}
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{sw x3, 19(x15)}
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{\tt%
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m16(rs1+sx(imm)) $\leftarrow$ rs2[31:0]\\
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pc $\leftarrow$ pc+4}
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{00000000111100011010100110100011}
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\TDrawInsnTypeIPicture
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{Add Immediate}
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{addi rd, rs1, imm}
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{addi x1, x7, 4}
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{\tt%
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rd $\leftarrow$ rs1+sx(imm)\\
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pc $\leftarrow$ pc+4}
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{00000000010000111000000010010011}
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\TDrawInsnTypeIPicture
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{Set Less Than Immediate}
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{slti rd, rs1, imm}
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{slti x1, x7, 4}
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{\tt%
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rd $\leftarrow$ (rs1 < sx(imm)) ? 1 : 0\\
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pc $\leftarrow$ pc+4}
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{00000000010000111010000010010011}
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\TDrawInsnTypeIPicture
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{Set Less Than Immediate Unsigned}
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{sltiu rd, rs1, imm}
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{sltiu x1, x7, 4}
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{\tt%
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rd $\leftarrow$ (rs1 < sx(imm)) ? 1 : 0\\
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pc $\leftarrow$ pc+4}
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{00000000010000111011000010010011}
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\TDrawInsnTypeIPicture
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{Exclusive Or Immediate}
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{xori rd, rs1, imm}
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{xori x1, x7, 4}
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{\tt%
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rd $\leftarrow$ rs1 \^{} sx(imm)\\
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pc $\leftarrow$ pc+4}
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{00000000010000111100000010010011}
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\TDrawInsnTypeIPicture
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{Or Immediate}
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{ori rd, rs1, imm}
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{ori x1, x7, 4}
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{\tt%
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rd $\leftarrow$ rs1 | sx(imm)\\
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pc $\leftarrow$ pc+4}
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{00000000010000111110000010010011}
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\TDrawInsnTypeIPicture
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{And Immediate}
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{andi rd, rs1, imm}
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{andi x1, x7, 4}
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{\tt%
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rd $\leftarrow$ rs1 \& sx(imm)\\
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pc $\leftarrow$ pc+4}
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{00000000010000111111000010010011}
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\TDrawInsnTypeRShiftPicture
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{Shift Left Logical Immediate}
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{slli rd, rs1, shamt}
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{slli x7, x3, 2}
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{\tt%
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rd $\leftarrow$ rs1 << shamt\\
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pc $\leftarrow$ pc+4}
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{00000000001000011001001110100011}
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\TDrawInsnTypeRShiftPicture
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{Shift Right Logical Immediate}
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{srli rd, rs1, shamt}
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{srli x7, x3, 2}
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{\tt%
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rd $\leftarrow$ rs1 >> shamt\\
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pc $\leftarrow$ pc+4}
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{00000000001000011101001110010011}
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\TDrawInsnTypeRShiftPicture
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{Shift Right Arithmetic Immediate}
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{srai rd, rs1, shamt}
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{srai x7, x3, 2}
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{\tt%
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rd $\leftarrow$ rs1 >> shamt\\
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pc $\leftarrow$ pc+4}
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{01000000001000011101001110010011}
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\TDrawInsnTypeRPicture
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{Add}
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{add rd, rs1, rs2}
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{add x7, x3, x31}
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{\tt%
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rd $\leftarrow$ rs1 + rs2\\
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pc $\leftarrow$ pc+4}
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{00000001111100011000001110110011}
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\TDrawInsnTypeRPicture
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{Subtract}
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{sub rd, rs1, rs2}
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{SUB x7, x3, x31}
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{\tt%
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rd $\leftarrow$ rs1 - rs2\\
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pc $\leftarrow$ pc+4}
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{01000001111100011000001110110011}
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\TDrawInsnTypeRPicture
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{Shift Left Logical}
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{sll rd, rs1, rs2}
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{sll x7, x3, x31}
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{\tt%
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rd $\leftarrow$ rs1 << rs2\\
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pc $\leftarrow$ pc+4}
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{00000001111100011001001110110011}
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\TDrawInsnTypeRPicture
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{Set Less Than}
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{slt rd, rs1, rs2}
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{slt x7, x3, x31}
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{\tt%
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rd $\leftarrow$ rs1 < rs2) ? 1 : 0\\
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pc $\leftarrow$ pc+4}
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{00000001111100011010001110110011}
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\TDrawInsnTypeRPicture
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{Set Less Than Unsigned}
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{sltu rd, rs1, rs2}
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{sltu x7, x3, x31}
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{\tt%
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rd $\leftarrow$ (rs1 < rs2) ? 1 : 0\\
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pc $\leftarrow$ pc+4}
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{00000001111100011011001110110011}
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\TDrawInsnTypeRPicture
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{Exclusive Or}
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{xor rd, rs1, rs2}
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{xor x7, x3, x31}
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{\tt%
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rd $\leftarrow$ rs1 \^{} rs2\\
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pc $\leftarrow$ pc+4}
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{00000001111100011100001110110011}
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\TDrawInsnTypeRPicture
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{Shift Right Logical}
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{srl rd, rs1, rs2}
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{srl x7, x3, x31}
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{\tt%
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rd $\leftarrow$ rs1 >> rs2\\
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pc $\leftarrow$ pc+4}
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{00000001111100011101001110110011}
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\TDrawInsnTypeRPicture
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{Shift Right Arithmetic}
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{sra rd, rs1, rs2}
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{sra x7, x3, x31}
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{\tt%
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rd $\leftarrow$ rs1 >> rs2\\
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pc $\leftarrow$ pc+4}
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{01000001111100011101001110110011}
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\TDrawInsnTypeRPicture
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{Or}
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{or rd, rs1, rs2}
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{or x7, x3, x31}
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{\tt%
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rd $\leftarrow$ rs1 | rs2\\
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pc $\leftarrow$ pc+4}
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{00000001111100011101001110110011}
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\TDrawInsnTypeRPicture
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{And}
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{and rd, rs1, rs2}
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{and x7, x3, x31}
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{\tt%
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rd $\leftarrow$ rs1 \& rs2\\
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pc $\leftarrow$ pc+4}
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{00000001111100011110001110110011}
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%\DrawInsnTypeFPicture{FENCE iorw, iorw}{00001111111100000000000000001111}
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%\DrawInsnTypeFPicture{FENCE.I}{00000000000000000001000000001111}
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%\DrawInsnTypeEPicture{ECALL}{00000000000000000000000001110011}
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%\DrawInsnTypeEPicture{EBREAK}{00000000000100000000000001110011}
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%\DrawInsnTypeCSPicture{CSRRW x3, 2, x15}{00000000001001111001000111110011}
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%\DrawInsnTypeCSPicture{CSRRS x3, 2, x15}{00000000001001111010000111110011}
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%\DrawInsnTypeCSPicture{CSRRC x3, 2, x15}{00000000001001111011000111110011}
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%\DrawInsnTypeCSIPicture{CSRRWI x3, 2, 7}{00000000001000111101000111110011}
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%\DrawInsnTypeCSIPicture{CSRRSI x3, 2, 7}{00000000001000111110000111110011}
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%\DrawInsnTypeCSIPicture{CSRRCI x3, 2, 7}{00000000001000111111000111110011}
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%\DrawInsnTypeRPicture{MUL x7, x3, x31}{00000011111100111000001110110011}
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%\DrawInsnTypeRPicture{MULH x7, x3, x31}{00000011111100111001001110110011}
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%\DrawInsnTypeRPicture{MULHS x7, x3, x31}{00000011111100111010001110110011}
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%\DrawInsnTypeRPicture{MULHU x7, x3, x31}{00000011111100111011001110110011}
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%\DrawInsnTypeRPicture{DIV x7, x3, x31}{00000011111100111100001110110011}
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%\DrawInsnTypeRPicture{DIVU x7, x3, x31}{00000011111100111101001110110011}
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%\DrawInsnTypeRPicture{REM x7, x3, x31}{00000011111100111110001110110011}
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%\DrawInsnTypeRPicture{REMU x7, x3, x31}{00000011111100111111001110110011}
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81
book/refcard/chapter.tex
Normal file
81
book/refcard/chapter.tex
Normal file
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|
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\chapter{RV32I Reference Card}
|
||||
|
||||
|
||||
\begin{tabular}{|ll|l|l|}
|
||||
\hline
|
||||
lui & t0, 3 & Load Upper Immediate & {\tt rd $\leftarrow$ zr(imm), pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
auipc & t0, 3 & Add Upper Immediate to PC & {\tt rd $\leftarrow$ pc + zr(imm), pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
jal & rd, imm & Jump And Link & {\tt{}rd $\leftarrow$ pc+4, pc $\leftarrow$ pc+sx(imm<<1)}\\
|
||||
\hline
|
||||
jalr & rd, rs1, imm & Jump And Link Register & {\tt{}rd $\leftarrow$ pc+4, pc $\leftarrow$ (rs1+sx(imm))\&\textasciitilde{}1}\\
|
||||
\hline
|
||||
beq & rs1, rs2, imm & Branch Equal & {\tt{}pc $\leftarrow$ \verb@(rs1==rs2) ? pc+sx(imm[12:1]<<1) : pc+4@}\\
|
||||
\hline
|
||||
bne & rs1, rs2, imm & Branch Not Equal & {\tt pc $\leftarrow$ (rs1!=rs2) ? pc+sx(imm[12:1]<<1) : pc+4}\\
|
||||
\hline
|
||||
blt & rs1, rs2, imm & Branch Less Than & {\tt pc $\leftarrow$ (rs1<rs2) ? pc+sx(imm[12:1]<<1) : pc+4}\\
|
||||
\hline
|
||||
bge & rs1, rs2, imm & Branch Greater or Equal & {\tt pc $\leftarrow$ (rs1>=rs2) ? pc+sx(imm[12:1]<<1) : pc+4}\\
|
||||
\hline
|
||||
bltu & rs1, rs2, imm & Branch Less Than Unsigned & {\tt pc $\leftarrow$ (rs1<rs2) ? pc+sx(imm[12:1]<<1) : pc+4}\\
|
||||
\hline
|
||||
bgeu & rs1, rs2, imm & Branch Greater or Equal Unsigned & {\tt pc $\leftarrow$ (rs1>=rs2) ? pc+sx(imm[12:1]<<1) : pc+4}\\
|
||||
\hline
|
||||
lb & rd, imm(rs1) & Load Byte & {\tt rd $\leftarrow$ sx(m8(rs1+sx(imm))), pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
lh & rd, imm(rs1) & Load Halfword & {\tt rd $\leftarrow$ sx(m16(rs1+sx(imm))), pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
lw & rd, imm(rs1) & Load Word & {\tt rd $\leftarrow$ sx(m32(rs1+sx(imm))), pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
lbu & rd, imm(rs1) & Load Byte Unsigned & {\tt rd $\leftarrow$ zx(m8(rs1+sx(imm))), pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
lhu & rd, imm(rs1) & Load Halfword Unsigned & {\tt rd $\leftarrow$ zx(m16(rs1+sx(imm))), pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
sb & rs2, imm(rs1) & Store Byte & {\tt m8(rs1+sx(imm)) $\leftarrow$ rs2[7:0], pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
sh & rs2, imm(rs1) & Store Halfword & {\tt m16(rs1+sx(imm)) $\leftarrow$ rs2[15:0], pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
sw & rs2, imm(rs1) & Store Word & {\tt m16(rs1+sx(imm)) $\leftarrow$ rs2[31:0], pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
addi & rd, rs1, imm & Add Immediate & {\tt rd $\leftarrow$ rs1+sx(imm), pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
slti & rd, rs1, imm & Set Less Than Immediate & {\tt rd $\leftarrow$ (rs1 < sx(imm)) ? 1 : 0, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
sltiu & rd, rs1, imm & Set Less Than Immediate Unsigned & {\tt rd $\leftarrow$ (rs1 < sx(imm)) ? 1 : 0, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
xori & rd, rs1, imm & Exclusive Or Immediate & {\tt rd $\leftarrow$ rs1 \^{} sx(imm), pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
ori & rd, rs1, imm & Or Immediate & {\tt rd $\leftarrow$ rs1 | sx(imm), pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
andi & rd, rs1, imm & And Immediate & {\tt rd $\leftarrow$ rs1 \& sx(imm), pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
slli & rd, rs1, shamt & Shift Left Logical Immediate & {\tt rd $\leftarrow$ rs1 << shamt, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
srli & rd, rs1, shamt & Shift Right Logical Immediate & {\tt rd $\leftarrow$ rs1 >> shamt, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
srai & rd, rs1, shamt & Shift Right Arithmetic Immediate & {\tt rd $\leftarrow$ rs1 >> shamt, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
add & rd, rs1, rs2 & Add & {\tt rd $\leftarrow$ rs1 + rs2, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
sub & rd, rs1, rs2 & Subtract & {\tt rd $\leftarrow$ rs1 - rs2, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
sll & rd, rs1, rs2 & Shift Left Logical & {\tt rd $\leftarrow$ rs1 << rs2, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
slt & rd, rs1, rs2 & Set Less Than & {\tt rd $\leftarrow$ rs1 < rs2) ? 1 : 0, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
sltu & rd, rs1, rs2 & Set Less Than Unsigned & {\tt rd $\leftarrow$ (rs1 < rs2) ? 1 : 0, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
xor & rd, rs1, rs2 & Exclusive Or & {\tt rd $\leftarrow$ rs1 \^{} rs2, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
srl & rd, rs1, rs2 & Shift Right Logical & {\tt rd $\leftarrow$ rs1 >> rs2, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
sra & rd, rs1, rs2 & Shift Right Arithmetic & {\tt rd $\leftarrow$ rs1 >> rs2, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
or & rd, rs1, rs2 & Or & {\tt rd $\leftarrow$ rs1 | rs2, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
and & rd, rs1, rs2 & And & {\tt rd $\leftarrow$ rs1 \& rs2, pc $\leftarrow$ pc+4}\\
|
||||
\hline
|
||||
\end{tabular}
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user