From f149f8c6d1e887450cffb96c821a6cbd337a252d Mon Sep 17 00:00:00 2001 From: John Winans Date: Sat, 12 May 2018 17:17:12 -0500 Subject: [PATCH] Spellcheck. --- book/amodes/chapter.tex | 25 +++++++++++++++++++++++++ book/binary/chapter.tex | 8 ++++---- book/elements/chapter.tex | 16 ++++++++-------- book/float/chapter.tex | 2 +- book/glossary.tex | 12 ++++++------ book/install/chapter.tex | 4 ++-- book/intro/chapter.tex | 24 ++++++++++++------------ book/rv32/chapter.tex | 4 ++-- book/toolchain/chapter.tex | 6 +++--- 9 files changed, 63 insertions(+), 38 deletions(-) create mode 100644 book/amodes/chapter.tex diff --git a/book/amodes/chapter.tex b/book/amodes/chapter.tex new file mode 100644 index 0000000..16b59f1 --- /dev/null +++ b/book/amodes/chapter.tex @@ -0,0 +1,25 @@ +\chapter{Addressing Modes} + + +A box showing +/- 2KB regions for \reg{gp} addressing with +LB, LBU, SB, LH, LHU, SH, LW, and SW instructions. + +\BeginTikzPicture + \draw(1.5,0) node{.data}; + \draw[->] (3,0) -- (4,0); % right arrow + + \draw(2,10) node{gp}; + \draw[->] (3,10) -- (4,10); % right arrow + + +% \draw(0,15) node{+2KB}; +% \draw(0,5) node{-2KB}; + \draw[->] (6,9) -- (6,1); % up arrow + \draw[->] (6,11) -- (6,19); % down arrow + + + \draw(6,20) node{\tt 0x8fff}; + \draw(6,10) node{\tt 0x8800}; + \draw(6,0) node{\tt 0x8000}; +\EndTikzPicture + diff --git a/book/binary/chapter.tex b/book/binary/chapter.tex index aef151b..28f745b 100644 --- a/book/binary/chapter.tex +++ b/book/binary/chapter.tex @@ -27,7 +27,7 @@ on a per-bit basis. %in that they do not impact neighboring bits. %by generating things like a carry or a borrow. When applied to multi-bit values, each bit position is operated upon -independantly of the other bits. +independently of the other bits. \enote{Need to define 1 as true and 0 as false somewhere.} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% @@ -529,7 +529,7 @@ To calculate $-4-8 = -12$ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Truncation and Overflow} -Disscuss the details of truncation and overflow here. +Discuss the details of truncation and overflow here. \enote{This chapter should be made consistent in its use of {\em truncation} and {\em overflow} as occur with signed and unsigned addition and subtraction.} @@ -600,10 +600,10 @@ be one beginning at any other address and is {\em illegal}. An attempt to fetch an instruction from an unaligned address will result in an error referred to as an alignment {\em \gls{exception}}. This and other exceptions cause the CPU to stop executing the -curent instruction and start executing a different set of instructions +current instruction and start executing a different set of instructions that are prepared to handle the problem. Often an exception is handled by completely stopping the program in a way that is commonly -refered to as a system or application {\em crash}. +referred to as a system or application {\em crash}. Given a properly aligned instruction address, the CPU can request that the main memory locate and deliver the values of the four bytes diff --git a/book/elements/chapter.tex b/book/elements/chapter.tex index 5339791..a7883bc 100644 --- a/book/elements/chapter.tex +++ b/book/elements/chapter.tex @@ -24,7 +24,7 @@ This program listing illustrates a number of things: \item A description of the listing's purpose appears under the name of the file. The description of \listingRef{zero4regs.S} is {\em Setting four registers to zero.} -\item The lines of the listing are numberd on the left margin for +\item The lines of the listing are numbered on the left margin for easy reference. \item An assembly program consists of lines of plain text. \item The RISC-V ISA does not provide an operation that will simply @@ -37,20 +37,20 @@ This program listing illustrates a number of things: into {\em machine language instructions.} \item Line 4 shows a {\em label} named {\em \_start}. The colon at the end is the indicator to the assembler that causes it to - recognize the preceeding characters as a label. + recognize the preceding characters as a label. \item Lines 5-8 are the four assembly language instructions that make up the program. Each instruction in this program consists of four {\em fields}. (Different instructions can have a different number of fields.) The fields on line 5 are: \begin{itemize} - \item [addi] The instruction mneumonic. It indicates the operation + \item [addi] The instruction mnemonic. It indicates the operation that the CPU will perform. \item [x28] The {\em destination} register that will receive the sum when the {\em addi} instruction is finished. The names of the 32 registers are expressed as x0 -- x31. \item [x0] One of the addends of the sum operation. (The x0 register - will always contain the vlaue zero. It can never be changed.) + will always contain the value zero. It can never be changed.) \item [0] The second addend is the number zero. \item [\# set \ldots] Any text anywhere in a RISC-V assembly language program that starts with the pound-sign is ignored by the assembler. @@ -68,7 +68,7 @@ This program listing illustrates a number of things: To illustrate what a CPU does when it executes instructions this text will use the \gls{rvddt} simulator to display shows sequence of events and the binary values involved. This simulator supports the RV32I ISA -and has a configurable ammount of memory.% +and has a configurable amount of memory.% \footnote{The {\em rvddt} simulator was written to generate the listings for this text. It is similar to the fancier {\em spike} simulator. Given the simplicity of the RV32I ISA, rvddt is less than 1700 lines of C++ @@ -88,7 +88,7 @@ in trace-mode. code into simulated memory at address 0. \item [$\ell$ 3] This line shows the prompt from the debugger and the command \verb@t4@ that the user entered to request that the simulator trace - the execution of four extructions. + the execution of four instructions. \item [$\ell$ 4-8] Prior to executing the first instruction, the state of the CPU registers is displayed. \item [$\ell$ 4] The values in registers 0, 1, 2, 3, 4, 5, 6 and 7 are printed @@ -113,13 +113,13 @@ in trace-mode. \gls{hexadecimal} form. \item [00000e13] The machine code of the instruction displayed in \gls{bigendian}, \gls{hexadecimal} form. - \item [addi] The mneumonic for the machine instruction. + \item [addi] The mnemonic for the machine instruction. \item [x28] The \reg{rd} field of the addi instruction. \item [x0] The \reg{rs1} field of the addi instruction that holds one of the two addends of the operation. \item [0] The \reg{imm} field of the addi instruction that holds the second of the two addends of the operation. - \item [\# \ldots] A simulator-generated comment that exaplains + \item [\# \ldots] A simulator-generated comment that explains what the instruction is doing. For this instruction it indicates that \reg{x28} will have the value zero stored into it as a result of performing the addition: $0+0$. diff --git a/book/float/chapter.tex b/book/float/chapter.tex index f835ba4..f0c277b 100644 --- a/book/float/chapter.tex +++ b/book/float/chapter.tex @@ -143,7 +143,7 @@ if we observe that the sign can be either 1 or 0. \item On the number-line, numbers between zero and the smallest fraction in either direction are in the {\em \gls{underflow}} areas. -\enote{Need to add the standard lecture numberline diagram showing +\enote{Need to add the standard lecture number-line diagram showing where the over/under-flow areas are and why.} \item On the number line, numbers greater than the mantissa of all-ones and the diff --git a/book/glossary.tex b/book/glossary.tex index 06c5afb..a9ba1c1 100644 --- a/book/glossary.tex +++ b/book/glossary.tex @@ -85,7 +85,7 @@ name=overflow, description={The situation where the result of an addition or subtraction operation is approaching positive or negative - infinity and exceeds the number of bits alloted to contain + infinity and exceeds the number of bits allotted to contain the result. This is typically caused by high-order truncation} } \newglossaryentry{underflow} @@ -93,7 +93,7 @@ name=underflow, description={The situation where the result of an addition or subtraction operation is approaching zero and exceeds the number - of bits alloted to contain the result. This is typically + of bits allotted to contain the result. This is typically caused by low-order truncation} } @@ -122,7 +122,7 @@ { name={alignment}, description={Refers to a range of numeric values that begin - at a multiple of some number. Primairly used when referring to + at a multiple of some number. Primarily used when referring to a memory address. For example an alignment of two refers to one or more addresses starting at even address and continuing onto subsequent adjacent, increasing memory addresses} @@ -157,12 +157,12 @@ simplicity of the Dynamic Debugging Tool (ddt) that was part of the CP/M operating system} } -\newglossaryentry{mneumonic} +\newglossaryentry{mnemonic} { - name={mneumonic}, + name={mnemonic}, description={A method used to remember something. In the case of assembly language, each machine instruction is given a name - so the programmer need not memorize the biary values of each + so the programmer need not memorize the binary values of each machine instruction} } \newglossaryentry{thread} diff --git a/book/install/chapter.tex b/book/install/chapter.tex index d213aff..63c8380 100644 --- a/book/install/chapter.tex +++ b/book/install/chapter.tex @@ -41,7 +41,7 @@ sudo chmod 777 /usr/local/riscv/ All other commands should be executed as a regular user. This will eliminate the possibility of clobbering system files that should not be touched when tinkering with -the toolchain applicaitons. +the toolchain applications. To download, compile and ``install'' the toolchain: @@ -69,4 +69,4 @@ Discuss rv32im and note that the details are found in \autoref{chapter:RV32}. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{rvddt} -Disciuss installing the rvddt simulator here. +Discuss installing the rvddt simulator here. diff --git a/book/intro/chapter.tex b/book/intro/chapter.tex index ca68643..54e6f1a 100644 --- a/book/intro/chapter.tex +++ b/book/intro/chapter.tex @@ -6,10 +6,10 @@ CPU executes a continuous stream of instructions called a \gls{program}. These program instructions are expressed in what is called \gls{MachineLanguage}. Each machine language instruction is a binary value. In order to provide a method to simplify the management of machine language -programs a symbolic mapping is provided where a \gls{mneumonic} can be used to +programs a symbolic mapping is provided where a \gls{mnemonic} can be used to specify each machine instruction and any of its parameters\ldots\ rather than require that programs be expressed as a series of binary values. -A set of mneumonics, parameters and rules for specifying their use for +A set of mnemonics, parameters and rules for specifying their use for the purpose of programming a CPU is called an {\em Assembly Language}. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% @@ -18,7 +18,7 @@ the purpose of programming a CPU is called an {\em Assembly Language}. There are different types of computers. A {\em digital} computer is the type that most people think of when they hear the word {\em computer}. -Other vareities of computers include {\em analog} and {\em quantum}. +Other varieties of computers include {\em analog} and {\em quantum}. A digital computer is one that that processes data that are represented using numeric values (digits), most commonly expressed in binary @@ -95,14 +95,14 @@ This text is not particularly concerned with non-volatile storage. The \acrshort{cpu} is a collection of registers and circuitry designed manipulate the register data and to exchange data and instructions with the storage system. The instructions that it reads from the main memory tells -the CPU to perform various mathamatical and logical operations on the data +the CPU to perform various mathematical and logical operations on the data in its registers and where to save the results of those operations. \subsubsection{Execution Unit} The part of a CPU that coordinates all aspects of the operations of each instruction is called the {\em execution unit.} It is what performs the transfers -of instructions and bata between the CPU and the main memory and tells the +of instructions and data between the CPU and the main memory and tells the registers when they are supposed to either store or recall data being transferred. The execution unit also controls the ALU (Arithmetic and Logic Unit). @@ -133,8 +133,8 @@ if it were otherwise a general purpose register.% {\em zero} register allows the total set of instructions that the CPU can execute to be simplified. Thus reducing its complexity, power consumption and cost.} -The \reg{pc} regiter is called the {\em program counter}. The CPU uses it to -remember the memory address where its program istructions are located. +The \reg{pc} register is called the {\em program counter}. The CPU uses it to +remember the memory address where its program instructions are located. The number of bits in each register is defined by the \acrfull{isa}. @@ -149,7 +149,7 @@ When more than one hart is present in a CPU, a different stream of instructions be executed on each hart all at the same time. Programs that are written to take advantage of this are called {\em multithreaded}. -This text will primairly focus on CPUs that have only one hart. +This text will primarily focus on CPUs that have only one hart. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% @@ -178,7 +178,7 @@ each binary instruction that a CPU can recognize and how it will process each one. The RISC-V ISA is defined as a set of modules. The purpose of -dividing the ISA into modules is to allow an implementor to select which +dividing the ISA into modules is to allow an implementer to select which features to incorporate into a CPU design. Any given RISC-V implementation must provide one of the {\em base} @@ -196,13 +196,13 @@ These base modules provide the minimal functional set of integer operations needed to execute a useful application. The differing bit-widths address the needs of different main-memory sizes. -This text primairly focuses on the RV32I base module and how to program it. +This text primarily focuses on the RV32I base module and how to program it. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Extension Modules} -RISC-V extension modules may be included by an implementor interested +RISC-V extension modules may be included by an implementer interested in optimizing a design for one or more purposes. \index{RV32M}% @@ -237,7 +237,7 @@ to an executing a program is the \reg{pc} register. The \reg{pc} contains the memory address containing the instruction that the CPU will execute next. For this to work, the instructions to be executed must have been previously -stored in ajacent main memory locations and the address of the first instruction +stored in adjacent main memory locations and the address of the first instruction placed into the \reg{pc} register. diff --git a/book/rv32/chapter.tex b/book/rv32/chapter.tex index 4bdab4d..fed9283 100644 --- a/book/rv32/chapter.tex +++ b/book/rv32/chapter.tex @@ -121,7 +121,7 @@ a 32-bit fullword. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\subsection{Sign Entended Left and Zero Extend Right} +\subsection{Sign Extended Left and Zero Extend Right} \label{extension:slzr} Some instructions such as the J-type (see \autoref{insnformat:jtype}) include @@ -546,7 +546,7 @@ boundaries.\cite[p.~68]{rvismv1v22:2017} Data alignment is not necessary but unaligned data can be inefficient. Accessing unaligned data using any of the load or store instructions can -also prevent a mempry access from operating +also prevent a memory access from operating atomically.~\cite[p.19]{rvismv1v22:2017} See also \autoref{RV32A}. diff --git a/book/toolchain/chapter.tex b/book/toolchain/chapter.tex index 3ec2b68..651ff78 100644 --- a/book/toolchain/chapter.tex +++ b/book/toolchain/chapter.tex @@ -4,17 +4,17 @@ This chapter discusses using the GNU toolchain elements to experiment with the material in this book. See \autoref{chapter:install} if you do not already have the -GNU crosscompiler toolchain availale on your system. +GNU crosscompiler toolchain available on your system. Discuss the choice of ilp32 as well as what the other variations would do. Discuss rv32im and note that the details are found in \autoref{chapter:RV32}. -Disciuss installing and using one of the RISC-V simulators +Discuss installing and using one of the RISC-V simulators here. -Describe the pre-processor, compiler, assemler and linker. +Describe the pre-processor, compiler, assembler and linker. Source, object, and binary files