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Fix figures for FENCE and CSRR insns.
This commit is contained in:
John Winans
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28378c4319
commit
f571cb705b
@ -446,6 +446,95 @@
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\DrawInsnTypeRTikz{#2}
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}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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% #1 the binary encoding
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\newcommand\DrawInsnTypeFTikz[1]{
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\BeginTikzPicture
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\StrLen{#1}[\numchars]
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\DrawInsnBitstring{\numchars}{#1}{FENCE}
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\DrawInsnBoxSeg{\numchars}{31}{28}{}
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\DrawInsnBoxSeg{\numchars}{27}{24}{pred}
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\DrawInsnBoxSeg{\numchars}{23}{20}{succ}
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\DrawInsnBoxSeg{\numchars}{19}{15}{}
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\DrawInsnBoxSeg{\numchars}{14}{12}{funct3}
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\DrawInsnBoxSeg{\numchars}{11}{7}{}
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\DrawInsnBoxSeg{\numchars}{6}{0}{opcode}
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\DrawHexMarkers{\numchars}
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\EndTikzPicture
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}
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\newcommand\DrawInsnTypeFPicture[2]{
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\InsnStatement{#1}\\
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\DrawInsnTypeFTikz{#2}
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}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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% #1 the binary encoding
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\newcommand\DrawInsnTypeETikz[1]{
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\BeginTikzPicture
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\StrLen{#1}[\numchars]
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\DrawInsnBitstring{\numchars}{#1}{\hyperref[insnformat:itype]{I-type}}
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\DrawInsnBoxSeg{\numchars}{31}{20}{}
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\DrawInsnBoxSeg{\numchars}{19}{15}{}
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\DrawInsnBoxSeg{\numchars}{14}{12}{funct3}
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\DrawInsnBoxSeg{\numchars}{11}{7}{}
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\DrawInsnBoxSeg{\numchars}{6}{0}{opcode}
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\DrawHexMarkers{\numchars}
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\EndTikzPicture
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}
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\newcommand\DrawInsnTypeEPicture[2]{
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\InsnStatement{#1}\\
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\DrawInsnTypeETikz{#2}
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}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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% #1 the binary encoding
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\newcommand\DrawInsnTypeCSTikz[1]{
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\BeginTikzPicture
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\StrLen{#1}[\numchars]
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\DrawInsnBitstring{\numchars}{#1}{\hyperref[insnformat:itype]{I-type}}
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\DrawInsnBoxSeg{\numchars}{31}{20}{csr}
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\DrawInsnBoxSeg{\numchars}{19}{15}{rs1}
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\DrawInsnBoxSeg{\numchars}{14}{12}{funct3}
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\DrawInsnBoxSeg{\numchars}{11}{7}{rd}
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\DrawInsnBoxSeg{\numchars}{6}{0}{opcode}
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\DrawHexMarkers{\numchars}
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\EndTikzPicture
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}
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\newcommand\DrawInsnTypeCSPicture[2]{
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\InsnStatement{#1}\\
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\DrawInsnTypeCSTikz{#2}
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}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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% #1 the binary encoding
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\newcommand\DrawInsnTypeCSITikz[1]{
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\BeginTikzPicture
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\StrLen{#1}[\numchars]
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\DrawInsnBitstring{\numchars}{#1}{\hyperref[insnformat:itype]{I-type}}
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\DrawInsnBoxSeg{\numchars}{31}{20}{csr}
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\DrawInsnBoxSeg{\numchars}{19}{15}{zimm}
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\DrawInsnBoxSeg{\numchars}{14}{12}{funct3}
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\DrawInsnBoxSeg{\numchars}{11}{7}{rd}
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\DrawInsnBoxSeg{\numchars}{6}{0}{opcode}
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\DrawHexMarkers{\numchars}
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\EndTikzPicture
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}
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\newcommand\DrawInsnTypeCSIPicture[2]{
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\InsnStatement{#1}\\
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\DrawInsnTypeCSITikz{#2}
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}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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@ -1464,6 +1464,7 @@ x7 = 0x00000322
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\subsection{FENCE predecessor, successor}
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\index{Instruction!FENCE}
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\enote{Which of the i, o, r and w goes into each bit? See what gas does.}%
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The FENCE instruction is used to order device I/O and memory accesses as
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viewed by other RISC-V harts and external devices or co-processors. Any
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combination of device input (I), device output (O), memory reads (R),
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@ -1486,11 +1487,7 @@ Operation:
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Encoding:
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%\insnTypeF{FENCE iorw, iorw}
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{0 0 0 1 1 1 1} % op
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{0 0 0} % funct3
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{1 1 1 1} % predecessor iorw
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{1 1 1 1} % successor iorw
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\DrawInsnTypeFPicture{FENCE iorw, iorw}{00001111111100000000000000001111}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{FENCE.I}
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@ -1515,11 +1512,7 @@ Operation:
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Encoding:
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%\insnTypeF{FENCE.I}
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{0 0 0 1 1 1 1} % op
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{0 0 1} % funct3
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{0 0 0 0} % predecessor iorw
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{0 0 0 0} % successor iorw
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\DrawInsnTypeFPicture{FENCE.I}{00000000000000000001000000001111}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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@ -1532,12 +1525,7 @@ for the system will define how parameters for the environment
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request are passed, but usually these will be in defined locations
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in the integer register file.~\cite[p.~24]{rvismv1v22:2017}
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%\insnTypeI{ECALL}
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{1 1 1 0 0 1 1}
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{0 0 0 0 0}
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{0 0 0}
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{0 0 0 0 0}
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{0 0 0 0 0 0 0 0 0 0 0 0}
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\DrawInsnTypeEPicture{ECALL}{00000000000000000000000001110011}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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@ -1547,12 +1535,7 @@ in the integer register file.~\cite[p.~24]{rvismv1v22:2017}
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The EBREAK instruction is used by debuggers to cause control to be
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transferred back to a debugging environment.~\cite[p.~24]{rvismv1v22:2017}
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%\insnTypeI{ECALL}
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{1 1 1 0 0 1 1}
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{0 0 0 0 0}
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{0 0 0}
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{0 0 0 0 0}
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{0 0 0 0 0 0 0 0 0 0 0 1}
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\DrawInsnTypeEPicture{EBREAK}{00000000000100000000000001110011}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{CSRRW rd, csr, rs1}
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@ -1565,12 +1548,7 @@ The initial value in rs1 is written to the CSR. If rd=x0, then the
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instruction shall not read the CSR and shall not cause any of the
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side-effects that might occur on a CSR read.~\cite[p.~22]{rvismv1v22:2017}
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%\insnTypeCSRR{CSRRW x3, 2, x15}
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{1 1 1 0 0 1 1} % op
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{0 0 0 1 1} % rd
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{0 0 1} % funct3
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{0 1 1 1 1} % rs1
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{0 0 0 0 0 0 0 0 0 0 1 0} % csr
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\DrawInsnTypeCSPicture{CSRRW x3, 2, x15}{00000000001001111001000111110011}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{CSRRS rd, csr, rs1}
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@ -1592,13 +1570,7 @@ register holding a zero value other than x0, the instruction will still
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attempt to write the unmodified value back to the CSR and will cause any
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attendant side effects.~\cite[p.~22]{rvismv1v22:2017}
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%\insnTypeCSRR{CSRRS x3, 2, x15}
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{1 1 1 0 0 1 1} % op
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{0 0 0 1 1} % rd
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{0 1 0} % funct3
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{0 1 1 1 1} % rs1
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{0 0 0 0 0 0 0 0 0 0 1 0} % csr
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\DrawInsnTypeCSPicture{CSRRS x3, 2, x15}{00000000001001111010000111110011}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{CSRRC rd, csr, rs1}
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@ -1620,14 +1592,7 @@ register holding a zero value other than x0, the instruction will still
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attempt to write the unmodified value back to the CSR and will cause any
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attendant side effects.~\cite[p.~22]{rvismv1v22:2017}
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%\insnTypeCSRR{CSRRC x3, 2, x15}
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{1 1 1 0 0 1 1} % op
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{0 0 0 1 1} % rd
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{0 1 1} % funct3
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{0 1 1 1 1} % rs1
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{0 0 0 0 0 0 0 0 0 0 1 0} % csr
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\DrawInsnTypeCSPicture{CSRRC x3, 2, x15}{00000000001001111011000111110011}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{CSRRWI rd, csr, imm}
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@ -1636,12 +1601,7 @@ attendant side effects.~\cite[p.~22]{rvismv1v22:2017}
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This instruction is the same as CSRRW except a 5-bit unsigned (zero-extended)
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immediate value is used rather than the value from a register.
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%\insnTypeCSRR{CSRRWI x3, 2, 7}
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{1 1 1 0 0 1 1} % op
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{0 0 0 1 1} % rd
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{1 0 1} % funct3
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{0 0 1 1 1} % imm
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{0 0 0 0 0 0 0 0 0 0 1 0} % csr
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\DrawInsnTypeCSIPicture{CSRRWI x3, 2, 7}{00000000001000111101000111110011}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{CSRRSI rd, csr, rs1}
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@ -1657,6 +1617,7 @@ the instruction shall not read the CSR and shall not cause any
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of the side-effects that might occur on a CSR
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read.~\cite[p.~22]{rvismv1v22:2017}
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\DrawInsnTypeCSIPicture{CSRRSI x3, 2, 7}{00000000001000111110000111110011}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{CSRRCI rd, csr, rs1}
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@ -1672,6 +1633,7 @@ the instruction shall not read the CSR and shall not cause any
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of the side-effects that might occur on a CSR
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read.~\cite[p.~22]{rvismv1v22:2017}
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\DrawInsnTypeCSIPicture{CSRRCI x3, 2, 7}{00000000001000111111000111110011}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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