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Fix figures for FENCE and CSRR insns.

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This commit is contained in:
John Winans 2018-05-07 18:31:12 -05:00
parent 28378c4319
commit f571cb705b
2 changed files with 100 additions and 49 deletions
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89
book/insnformats.tex
View File

@ -446,6 +446,95 @@
\DrawInsnTypeRTikz{#2} \DrawInsnTypeRTikz{#2}
} }
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% #1 the binary encoding
\newcommand\DrawInsnTypeFTikz[1]{
\BeginTikzPicture
\StrLen{#1}[\numchars]
\DrawInsnBitstring{\numchars}{#1}{FENCE}
\DrawInsnBoxSeg{\numchars}{31}{28}{}
\DrawInsnBoxSeg{\numchars}{27}{24}{pred}
\DrawInsnBoxSeg{\numchars}{23}{20}{succ}
\DrawInsnBoxSeg{\numchars}{19}{15}{}
\DrawInsnBoxSeg{\numchars}{14}{12}{funct3}
\DrawInsnBoxSeg{\numchars}{11}{7}{}
\DrawInsnBoxSeg{\numchars}{6}{0}{opcode}
\DrawHexMarkers{\numchars}
\EndTikzPicture
}
\newcommand\DrawInsnTypeFPicture[2]{
\InsnStatement{#1}\\
\DrawInsnTypeFTikz{#2}
}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% #1 the binary encoding
\newcommand\DrawInsnTypeETikz[1]{
\BeginTikzPicture
\StrLen{#1}[\numchars]
\DrawInsnBitstring{\numchars}{#1}{\hyperref[insnformat:itype]{I-type}}
\DrawInsnBoxSeg{\numchars}{31}{20}{}
\DrawInsnBoxSeg{\numchars}{19}{15}{}
\DrawInsnBoxSeg{\numchars}{14}{12}{funct3}
\DrawInsnBoxSeg{\numchars}{11}{7}{}
\DrawInsnBoxSeg{\numchars}{6}{0}{opcode}
\DrawHexMarkers{\numchars}
\EndTikzPicture
}
\newcommand\DrawInsnTypeEPicture[2]{
\InsnStatement{#1}\\
\DrawInsnTypeETikz{#2}
}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% #1 the binary encoding
\newcommand\DrawInsnTypeCSTikz[1]{
\BeginTikzPicture
\StrLen{#1}[\numchars]
\DrawInsnBitstring{\numchars}{#1}{\hyperref[insnformat:itype]{I-type}}
\DrawInsnBoxSeg{\numchars}{31}{20}{csr}
\DrawInsnBoxSeg{\numchars}{19}{15}{rs1}
\DrawInsnBoxSeg{\numchars}{14}{12}{funct3}
\DrawInsnBoxSeg{\numchars}{11}{7}{rd}
\DrawInsnBoxSeg{\numchars}{6}{0}{opcode}
\DrawHexMarkers{\numchars}
\EndTikzPicture
}
\newcommand\DrawInsnTypeCSPicture[2]{
\InsnStatement{#1}\\
\DrawInsnTypeCSTikz{#2}
}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% #1 the binary encoding
\newcommand\DrawInsnTypeCSITikz[1]{
\BeginTikzPicture
\StrLen{#1}[\numchars]
\DrawInsnBitstring{\numchars}{#1}{\hyperref[insnformat:itype]{I-type}}
\DrawInsnBoxSeg{\numchars}{31}{20}{csr}
\DrawInsnBoxSeg{\numchars}{19}{15}{zimm}
\DrawInsnBoxSeg{\numchars}{14}{12}{funct3}
\DrawInsnBoxSeg{\numchars}{11}{7}{rd}
\DrawInsnBoxSeg{\numchars}{6}{0}{opcode}
\DrawHexMarkers{\numchars}
\EndTikzPicture
}
\newcommand\DrawInsnTypeCSIPicture[2]{
\InsnStatement{#1}\\
\DrawInsnTypeCSITikz{#2}
}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

60
book/rv32/chapter.tex
View File

@ -1464,6 +1464,7 @@ x7 = 0x00000322
\subsection{FENCE predecessor, successor} \subsection{FENCE predecessor, successor}
\index{Instruction!FENCE} \index{Instruction!FENCE}
\enote{Which of the i, o, r and w goes into each bit? See what gas does.}%
The FENCE instruction is used to order device I/O and memory accesses as The FENCE instruction is used to order device I/O and memory accesses as
viewed by other RISC-V harts and external devices or co-processors. Any viewed by other RISC-V harts and external devices or co-processors. Any
combination of device input (I), device output (O), memory reads (R), combination of device input (I), device output (O), memory reads (R),
@ -1486,11 +1487,7 @@ Operation:
Encoding: Encoding:
%\insnTypeF{FENCE iorw, iorw} \DrawInsnTypeFPicture{FENCE iorw, iorw}{00001111111100000000000000001111}
{0 0 0 1 1 1 1} % op
{0 0 0} % funct3
{1 1 1 1} % predecessor iorw
{1 1 1 1} % successor iorw
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{FENCE.I} \subsection{FENCE.I}
@ -1515,11 +1512,7 @@ Operation:
Encoding: Encoding:
%\insnTypeF{FENCE.I} \DrawInsnTypeFPicture{FENCE.I}{00000000000000000001000000001111}
{0 0 0 1 1 1 1} % op
{0 0 1} % funct3
{0 0 0 0} % predecessor iorw
{0 0 0 0} % successor iorw
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
@ -1532,12 +1525,7 @@ for the system will define how parameters for the environment
request are passed, but usually these will be in defined locations request are passed, but usually these will be in defined locations
in the integer register file.~\cite[p.~24]{rvismv1v22:2017} in the integer register file.~\cite[p.~24]{rvismv1v22:2017}
%\insnTypeI{ECALL} \DrawInsnTypeEPicture{ECALL}{00000000000000000000000001110011}
{1 1 1 0 0 1 1}
{0 0 0 0 0}
{0 0 0}
{0 0 0 0 0}
{0 0 0 0 0 0 0 0 0 0 0 0}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
@ -1547,12 +1535,7 @@ in the integer register file.~\cite[p.~24]{rvismv1v22:2017}
The EBREAK instruction is used by debuggers to cause control to be The EBREAK instruction is used by debuggers to cause control to be
transferred back to a debugging environment.~\cite[p.~24]{rvismv1v22:2017} transferred back to a debugging environment.~\cite[p.~24]{rvismv1v22:2017}
%\insnTypeI{ECALL} \DrawInsnTypeEPicture{EBREAK}{00000000000100000000000001110011}
{1 1 1 0 0 1 1}
{0 0 0 0 0}
{0 0 0}
{0 0 0 0 0}
{0 0 0 0 0 0 0 0 0 0 0 1}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{CSRRW rd, csr, rs1} \subsection{CSRRW rd, csr, rs1}
@ -1565,12 +1548,7 @@ The initial value in rs1 is written to the CSR. If rd=x0, then the
instruction shall not read the CSR and shall not cause any of the instruction shall not read the CSR and shall not cause any of the
side-effects that might occur on a CSR read.~\cite[p.~22]{rvismv1v22:2017} side-effects that might occur on a CSR read.~\cite[p.~22]{rvismv1v22:2017}
%\insnTypeCSRR{CSRRW x3, 2, x15} \DrawInsnTypeCSPicture{CSRRW x3, 2, x15}{00000000001001111001000111110011}
{1 1 1 0 0 1 1} % op
{0 0 0 1 1} % rd
{0 0 1} % funct3
{0 1 1 1 1} % rs1
{0 0 0 0 0 0 0 0 0 0 1 0} % csr
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{CSRRS rd, csr, rs1} \subsection{CSRRS rd, csr, rs1}
@ -1592,13 +1570,7 @@ register holding a zero value other than x0, the instruction will still
attempt to write the unmodified value back to the CSR and will cause any attempt to write the unmodified value back to the CSR and will cause any
attendant side effects.~\cite[p.~22]{rvismv1v22:2017} attendant side effects.~\cite[p.~22]{rvismv1v22:2017}
\DrawInsnTypeCSPicture{CSRRS x3, 2, x15}{00000000001001111010000111110011}
%\insnTypeCSRR{CSRRS x3, 2, x15}
{1 1 1 0 0 1 1} % op
{0 0 0 1 1} % rd
{0 1 0} % funct3
{0 1 1 1 1} % rs1
{0 0 0 0 0 0 0 0 0 0 1 0} % csr
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{CSRRC rd, csr, rs1} \subsection{CSRRC rd, csr, rs1}
@ -1620,14 +1592,7 @@ register holding a zero value other than x0, the instruction will still
attempt to write the unmodified value back to the CSR and will cause any attempt to write the unmodified value back to the CSR and will cause any
attendant side effects.~\cite[p.~22]{rvismv1v22:2017} attendant side effects.~\cite[p.~22]{rvismv1v22:2017}
%\insnTypeCSRR{CSRRC x3, 2, x15} \DrawInsnTypeCSPicture{CSRRC x3, 2, x15}{00000000001001111011000111110011}
{1 1 1 0 0 1 1} % op
{0 0 0 1 1} % rd
{0 1 1} % funct3
{0 1 1 1 1} % rs1
{0 0 0 0 0 0 0 0 0 0 1 0} % csr
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{CSRRWI rd, csr, imm} \subsection{CSRRWI rd, csr, imm}
@ -1636,12 +1601,7 @@ attendant side effects.~\cite[p.~22]{rvismv1v22:2017}
This instruction is the same as CSRRW except a 5-bit unsigned (zero-extended) This instruction is the same as CSRRW except a 5-bit unsigned (zero-extended)
immediate value is used rather than the value from a register. immediate value is used rather than the value from a register.
%\insnTypeCSRR{CSRRWI x3, 2, 7} \DrawInsnTypeCSIPicture{CSRRWI x3, 2, 7}{00000000001000111101000111110011}
{1 1 1 0 0 1 1} % op
{0 0 0 1 1} % rd
{1 0 1} % funct3
{0 0 1 1 1} % imm
{0 0 0 0 0 0 0 0 0 0 1 0} % csr
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{CSRRSI rd, csr, rs1} \subsection{CSRRSI rd, csr, rs1}
@ -1657,6 +1617,7 @@ the instruction shall not read the CSR and shall not cause any
of the side-effects that might occur on a CSR of the side-effects that might occur on a CSR
read.~\cite[p.~22]{rvismv1v22:2017} read.~\cite[p.~22]{rvismv1v22:2017}
\DrawInsnTypeCSIPicture{CSRRSI x3, 2, 7}{00000000001000111110000111110011}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{CSRRCI rd, csr, rs1} \subsection{CSRRCI rd, csr, rs1}
@ -1672,6 +1633,7 @@ the instruction shall not read the CSR and shall not cause any
of the side-effects that might occur on a CSR of the side-effects that might occur on a CSR
read.~\cite[p.~22]{rvismv1v22:2017} read.~\cite[p.~22]{rvismv1v22:2017}
\DrawInsnTypeCSIPicture{CSRRCI x3, 2, 7}{00000000001000111111000111110011}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%