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93 lines
7.5 KiB
TeX
93 lines
7.5 KiB
TeX
\chapter{RV32I Reference Card}
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{
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\small
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\begin{tabular}{|ll|c|l|l|}
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\hline
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\multicolumn{2}{|c|}{Usage Template} & Type & Description & Detailed Description \\
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\hline
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\hline
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add & rd, rs1, rs2 & \hyperref[insnformat:rtype]{R} & \hyperref[insn:add]{Add} & {\tt rd $\leftarrow$ rs1 + rs2, pc $\leftarrow$ pc+4}\\
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\hline
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addi & rd, rs1, imm & \hyperref[insnformat:itype]{I} & \hyperref[insn:addi]{Add Immediate} & {\tt rd $\leftarrow$ rs1 + \hyperref[imm.i:decode]{imm\_i}, pc $\leftarrow$ pc+4}\\
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\hline
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and & rd, rs1, rs2 & \hyperref[insnformat:rtype]{R} & \hyperref[insn:and]{And} & {\tt rd $\leftarrow$ rs1 \& rs2, pc $\leftarrow$ pc+4}\\
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\hline
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andi & rd, rs1, imm & \hyperref[insnformat:itype]{I} & \hyperref[insn:andi]{And Immediate} & {\tt rd $\leftarrow$ rs1 \& \hyperref[imm.i:decode]{imm\_i}, pc $\leftarrow$ pc+4}\\
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\hline
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auipc & rd, imm & \hyperref[insnformat:utype]{U} & \hyperref[insn:auipc]{Add Upper Immediate to PC} & {\tt rd $\leftarrow$ pc + \hyperref[imm.u:decode]{imm\_u}, pc $\leftarrow$ pc+4}\\
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\hline
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beq & rs1, rs2, pcrel\_13 & \hyperref[insnformat:btype]{B} & \hyperref[insn:beq]{Branch Equal} & {\tt pc $\leftarrow$ pc + (\verb@(rs1==rs2) ? @\hyperref[imm.b:decode]{imm\_b}\verb@ : 4@)}\\
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\hline
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bge & rs1, rs2, pcrel\_13 & \hyperref[insnformat:btype]{B} & \hyperref[insn:bge]{Branch Greater or Equal} & {\tt pc $\leftarrow$ pc + (\verb@(rs1>=rs2) ? @\hyperref[imm.b:decode]{imm\_b}\verb@ : 4@)}\\
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\hline
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bgeu & rs1, rs2, pcrel\_13 & \hyperref[insnformat:btype]{B} & \hyperref[insn:bgeu]{Branch Greater or Equal Unsigned} & {\tt pc $\leftarrow$ pc + (\verb@(rs1>=rs2) ? @\hyperref[imm.b:decode]{imm\_b}\verb@ : 4@)}\\
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\hline
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blt & rs1, rs2, pcrel\_13 & \hyperref[insnformat:btype]{B} & \hyperref[insn:blt]{Branch Less Than} & {\tt pc $\leftarrow$ pc + (\verb@(rs1<rs2) ? @\hyperref[imm.b:decode]{imm\_b}\verb@ : 4@)}\\
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\hline
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bltu & rs1, rs2, pcrel\_13 & \hyperref[insnformat:btype]{B} & \hyperref[insn:bltu]{Branch Less Than Unsigned} & {\tt pc $\leftarrow$ pc + (\verb@(rs1<rs2) ? @\hyperref[imm.b:decode]{imm\_b}\verb@ : 4@)}\\
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\hline
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bne & rs1, rs2, pcrel\_13 & \hyperref[insnformat:btype]{B} & \hyperref[insn:bne]{Branch Not Equal} & {\tt pc $\leftarrow$ pc + (\verb@(rs1!=rs2) ? @\hyperref[imm.b:decode]{imm\_b}\verb@ : 4@)}\\
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\hline
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jal & rd, pcrel\_21 & \hyperref[insnformat:jtype]{J} & \hyperref[insn:jal]{Jump And Link} & {\tt rd $\leftarrow$ pc+4, pc $\leftarrow$ pc+\hyperref[imm.j:decode]{imm\_j}}\\
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jalr & rd, imm(rs1) & \hyperref[insnformat:itype]{I} & \hyperref[insn:jalr]{Jump And Link Register} & {\tt rd $\leftarrow$ pc+4, pc $\leftarrow$ (rs1+\hyperref[imm.i:decode]{imm\_i})\&\textasciitilde{}1}\\
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lb & rd, imm(rs1) & \hyperref[insnformat:itype]{I} & \hyperref[insn:lb]{Load Byte} & {\tt rd $\leftarrow$ sx(m8(rs1+\hyperref[imm.i:decode]{imm\_i})), pc $\leftarrow$ pc+4}\\
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lbu & rd, imm(rs1) & \hyperref[insnformat:itype]{I} & \hyperref[insn:lbu]{Load Byte Unsigned} & {\tt rd $\leftarrow$ zx(m8(rs1+\hyperref[imm.i:decode]{imm\_i})), pc $\leftarrow$ pc+4}\\
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\hline
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lh & rd, imm(rs1) & \hyperref[insnformat:itype]{I} & \hyperref[insn:lh]{Load Halfword} & {\tt rd $\leftarrow$ sx(m16(rs1+\hyperref[imm.i:decode]{imm\_i})), pc $\leftarrow$ pc+4}\\
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\hline
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lhu & rd, imm(rs1) & \hyperref[insnformat:itype]{I} & \hyperref[insn:lhu]{Load Halfword Unsigned} & {\tt rd $\leftarrow$ zx(m16(rs1+\hyperref[imm.i:decode]{imm\_i})), pc $\leftarrow$ pc+4}\\
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lui & rd, imm & \hyperref[insnformat:utype]{U} & \hyperref[insn:lui]{Load Upper Immediate} & {\tt rd $\leftarrow$ \hyperref[imm.u:decode]{imm\_u}, pc $\leftarrow$ pc+4}\\
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lw & rd, imm(rs1) & \hyperref[insnformat:itype]{I} & \hyperref[insn:lw]{Load Word} & {\tt rd $\leftarrow$ sx(m32(rs1+\hyperref[imm.i:decode]{imm\_i})), pc $\leftarrow$ pc+4}\\
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\hline
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or & rd, rs1, rs2 & \hyperref[insnformat:rtype]{R} & \hyperref[insn:or]{Or} & {\tt rd $\leftarrow$ rs1 | rs2, pc $\leftarrow$ pc+4}\\
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\hline
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ori & rd, rs1, imm & \hyperref[insnformat:itype]{I} & \hyperref[insn:ori]{Or Immediate} & {\tt rd $\leftarrow$ rs1 | \hyperref[imm.i:decode]{imm\_i}, pc $\leftarrow$ pc+4}\\
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sb & rs2, imm(rs1) & \hyperref[insnformat:stype]{S} & \hyperref[insn:sb]{Store Byte} & {\tt m8(rs1+\hyperref[imm.s:decode]{imm\_s}) $\leftarrow$ rs2[7:0], pc $\leftarrow$ pc+4}\\
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\hline
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sh & rs2, imm(rs1) & \hyperref[insnformat:stype]{S} & \hyperref[insn:sh]{Store Halfword} & {\tt m16(rs1+\hyperref[imm.s:decode]{imm\_s}) $\leftarrow$ rs2[15:0], pc $\leftarrow$ pc+4}\\
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\hline
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sll & rd, rs1, rs2 & \hyperref[insnformat:rtype]{R} & \hyperref[insn:sll]{Shift Left Logical} & {\tt rd $\leftarrow$ rs1 << (rs2\%XLEN), pc $\leftarrow$ pc+4}\\
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\hline
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slli & rd, rs1, shamt & \hyperref[insnformat:itype]{I} & \hyperref[insn:slli]{Shift Left Logical Immediate} & {\tt rd $\leftarrow$ rs1 << \hyperref[shamt.i:decode]{shamt\_i}, pc $\leftarrow$ pc+4}\\
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\hline
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slt & rd, rs1, rs2 & \hyperref[insnformat:rtype]{R} & \hyperref[insn:slt]{Set Less Than} & {\tt rd $\leftarrow$ (rs1 < rs2) ? 1 : 0, pc $\leftarrow$ pc+4}\\
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\hline
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slti & rd, rs1, imm & \hyperref[insnformat:itype]{I} & \hyperref[insn:slti]{Set Less Than Immediate} & {\tt rd $\leftarrow$ (rs1 < \hyperref[imm.i:decode]{imm\_i}) ? 1 : 0, pc $\leftarrow$ pc+4}\\
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\hline
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sltiu & rd, rs1, imm & \hyperref[insnformat:itype]{I} & \hyperref[insn:sltiu]{Set Less Than Immediate Unsigned} & {\tt rd $\leftarrow$ (rs1 < \hyperref[imm.i:decode]{imm\_i}) ? 1 : 0, pc $\leftarrow$ pc+4}\\
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\hline
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sltu & rd, rs1, rs2 & \hyperref[insnformat:rtype]{R} & \hyperref[insn:sltu]{Set Less Than Unsigned} & {\tt rd $\leftarrow$ (rs1 < rs2) ? 1 : 0, pc $\leftarrow$ pc+4}\\
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\hline
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sra & rd, rs1, rs2 & \hyperref[insnformat:rtype]{R} & \hyperref[insn:sra]{Shift Right Arithmetic} & {\tt rd $\leftarrow$ rs1 >> (rs2\%XLEN), pc $\leftarrow$ pc+4}\\
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\hline
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srai & rd, rs1, shamt & \hyperref[insnformat:itype]{I} & \hyperref[insn:srai]{Shift Right Arithmetic Immediate} & {\tt rd $\leftarrow$ rs1 >> \hyperref[shamt.i:decode]{shamt\_i}, pc $\leftarrow$ pc+4}\\
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srl & rd, rs1, rs2 & \hyperref[insnformat:rtype]{R} & \hyperref[insn:srl]{Shift Right Logical} & {\tt rd $\leftarrow$ rs1 >> (rs2\%XLEN), pc $\leftarrow$ pc+4}\\
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srli & rd, rs1, shamt & \hyperref[insnformat:itype]{I} & \hyperref[insn:srli]{Shift Right Logical Immediate} & {\tt rd $\leftarrow$ rs1 >> \hyperref[shamt.i:decode]{shamt\_i}, pc $\leftarrow$ pc+4}\\
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sub & rd, rs1, rs2 & \hyperref[insnformat:rtype]{R} & \hyperref[insn:sub]{Subtract} & {\tt rd $\leftarrow$ rs1 - rs2, pc $\leftarrow$ pc+4}\\
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sw & rs2, imm(rs1) & \hyperref[insnformat:stype]{S} & \hyperref[insn:sw]{Store Word} & {\tt m32(rs1+\hyperref[imm.s:decode]{imm\_s}) $\leftarrow$ rs2[31:0], pc $\leftarrow$ pc+4}\\
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xor & rd, rs1, rs2 & \hyperref[insnformat:rtype]{R} & \hyperref[insn:xor]{Exclusive Or} & {\tt rd $\leftarrow$ rs1 \^{} rs2, pc $\leftarrow$ pc+4}\\
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xori & rd, rs1, imm & \hyperref[insnformat:itype]{I} & \hyperref[insn:xori]{Exclusive Or Immediate} & {\tt rd $\leftarrow$ rs1 \^{} \hyperref[imm.i:decode]{imm\_i}, pc $\leftarrow$ pc+4}\\
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\hline
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\end{tabular}
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}
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\newpage
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{\Large RV32I Base Instruction Set Encoding}~\cite[p.~104]{rvismv1v22:2017}
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%\DrawAllInsnTypes\\
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\DrawAllInsnOps
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