mirror of
https://github.com/wichtounet/thor-os.git
synced 2025-09-16 16:11:42 -04:00
Complete cpuid
This commit is contained in:
Baptiste Wicht
parent
4c5571508f
commit
fab6fb46b5
@ -5,27 +5,28 @@
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// http://www.boost.org/LICENSE_1_0.txt)
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//=======================================================================
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#include <string.hpp>
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#include <print.hpp>
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#include <system.hpp>
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namespace {
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void native_cpuid(uint32_t key, uint32_t* eax, uint32_t* ebx, uint32_t* ecx, uint32_t* edx){
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*eax = key;
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inline void native_cpuid(uint32_t key, uint32_t& eax, uint32_t& ebx, uint32_t& ecx, uint32_t& edx){
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eax = key;
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/* ecx is often an input as well as an output. */
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__asm__ __volatile__("cpuid"
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: "=a" (*eax),
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"=b" (*ebx),
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"=c" (*ecx),
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"=d" (*edx)
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: "0" (*eax), "2" (*ecx));
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asm volatile("cpuid"
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: "=a" (eax),
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"=b" (ebx),
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"=c" (ecx),
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"=d" (edx)
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: "a" (eax), "c" (ecx));
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}
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void get_base_info(){
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uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
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native_cpuid(1, &eax, &ebx, &ecx, &edx);
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native_cpuid(1, eax, ebx, ecx, edx);
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printf("Stepping: %u\n", eax & 0xF);
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printf("Model: %u\n", (eax >> 4) & 0xF);
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@ -35,10 +36,319 @@ void get_base_info(){
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printf("Extended Family: %u\n", (eax >> 20) & 0xFF);
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}
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void get_vendor_id(){
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uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
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native_cpuid(0, eax, ebx, ecx, edx);
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uint32_t vendor_id[3];
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vendor_id[0] = ebx;
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vendor_id[1] = edx;
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vendor_id[2] = ecx;
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printf("Vendor ID: %s\n", reinterpret_cast<const char*>(vendor_id));
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}
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void get_brand_string(){
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uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
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uint32_t brand_string[12];
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native_cpuid(0x80000002, eax, ebx, ecx, edx);
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brand_string[0] = eax;
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brand_string[1] = ebx;
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brand_string[2] = ecx;
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brand_string[3] = edx;
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native_cpuid(0x80000003, eax, ebx, ecx, edx);
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brand_string[4] = eax;
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brand_string[5] = ebx;
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brand_string[6] = ecx;
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brand_string[7] = edx;
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native_cpuid(0x80000004, eax, ebx, ecx, edx);
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brand_string[8] = eax;
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brand_string[9] = ebx;
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brand_string[10] = ecx;
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brand_string[11] = edx;
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printf("Brand String: %s\n", reinterpret_cast<const char*>(brand_string));
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}
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// EDX Features
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const int FPU = 1 << 0;
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const int MMX = 1 << 23;
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const int SSE = 1 << 25;
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const int SSE2 = 1 << 26;
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const int HT = 1 << 28;
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//EAX Features
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const int SSE3 = 1 << 9;
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const int SSE41 = 1 << 19;
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const int SSE42 = 1 << 20;
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const int AES = 1 << 25;
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const int AVX = 1 << 28;
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void test_feature(uint32_t reg, int mask, const char* s){
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if(reg & mask){
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print(' ');
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print(s);
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}
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}
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void get_features(){
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uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
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native_cpuid(1, eax, ebx, ecx, edx);
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print("Features:");
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test_feature(edx, FPU, "fpu");
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test_feature(edx, MMX, "mmx");
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test_feature(edx, SSE, "sse");
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test_feature(edx, SSE2, "sse2");
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test_feature(edx, HT, "ht");
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test_feature(ecx, SSE3, "sse3");
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test_feature(ecx, SSE41, "sse4_1");
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test_feature(ecx, SSE42, "sse4_2");
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test_feature(ecx, AES, "aes");
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test_feature(ecx, AVX, "avx");
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print_line();
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}
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void decode_bytes (int data, int descriptor[16], int *next){
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int i;
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i = *next;
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if (!(data & 0x80000000)) {
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descriptor[i++] = data & 0x000000FF;
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descriptor[i++] = (data & 0x0000FF00) / 256; // 1 bytes R
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descriptor[i++] = (data & 0x00FF0000) / 65536; // 2 bytes R
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descriptor[i++] = (data & 0xFF000000) / 16777216; // 3 bytes R
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*next = i;
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}
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}
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void get_cache_info() {
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int next = 0, i = 0;
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int descriptor[256];
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int mem_count;
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uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
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print_line("Cache and TLB:");
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native_cpuid(0, eax, ebx, ecx, edx);
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if (eax < 2){
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print_line(" CPUID(2) not supported");
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return;
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}
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native_cpuid(2, eax, ebx, ecx, edx);
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mem_count = eax & 0x000000FF; // 1st byte is the count
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eax &= 0xFFFFFF00; // mask off the count
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int* desc = descriptor;
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while ( i < mem_count) {
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decode_bytes(eax, desc, &next);
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decode_bytes(ebx, desc, &next);
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decode_bytes(ecx, desc, &next);
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decode_bytes(edx, desc, &next);
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++i;
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ecx = i;
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native_cpuid(2, eax, ebx, ecx, edx);
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desc += 16;
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}
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for (i=0; i< next; i++) {
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if ( descriptor[i] == 0x00){
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// NULL descriptor, legal value but no info
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continue;
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}
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if ( descriptor[i] == 0x01)
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print_line(" Instruction TLB ... 4 kb pages, 4-way associative, 32 entries");
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if ( descriptor[i] == 0x02)
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print_line(" Instruction TLB ... 4 Mb pages, 4-way associative, 2 entries");
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if ( descriptor[i] == 0x03)
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print_line(" Data TLB .......... 4 kb pages, 4-way associative, 64 entries");
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if ( descriptor[i] == 0x04)
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print_line(" Data TLB .......... 4 Mb pages, 4-way associative, 8 entries");
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if ( descriptor[i] == 0x06)
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print_line(" L1 instruction cache 8 kb, 4-way associative, 32 byte line size");
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if ( descriptor[i] == 0x08)
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print_line(" L1 instruction cache 16 kb, 4-way associative, 32 byte line size");
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if ( descriptor[i] == 0x0A)
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print_line(" L1 data cache ..... 8 kb, 2-way associative, 32 byte line size");
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if ( descriptor[i] == 0x0B)
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print_line(" Instruction TLB ... 4 Mb pages, 4-way associative, 4 entries");
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if ( descriptor[i] == 0x0C)
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print_line(" L1 data cache ..... 16 kb, 4-way associative, 32 byte line size");
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if ( descriptor[i] == 0x22){
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print_line(" L3 cache: 512K Bytes, 4-way associative, 64 byte line size, ");
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print_line(" 128 byte sector size" );
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}
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if ( descriptor[i] == 0x23){
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print_line(" L3 cache: 1M Bytes, 8-way associative, 64 byte line size, ");
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print_line(" 128 byte sector size" );
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}
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if ( descriptor[i] == 0x25){
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print_line(" L3 cache: 2M Bytes, 8-way associative, 64 byte line size, ");
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print_line(" 128 byte sector size" );
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}
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if ( descriptor[i] == 0x29){
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print_line(" L3 cache: 4M Bytes, 8-way associative, 64 byte line size, ");
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print_line(" 128 byte sector size" );
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}
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if ( descriptor[i] == 0x2C)
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print_line(" 1st-level D-cache: 32K Bytes, 8-way associative, 64 byte line size");
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if ( descriptor[i] == 0x30)
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print_line(" 1st-level I-cache: 32K Bytes, 8-way associative, 64 byte line size");
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if ( descriptor[i] == 0x40)
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print_line(" No L2 cache OR if there is an L2 cache, then no L3 cache");
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if ( descriptor[i] == 0x41)
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print_line(" L2 cache .......... 128 kb, 4-way associative, 32 byte line size");
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if ( descriptor[i] == 0x42)
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print_line(" L2 cache .......... 256 kb, 4-way associative, 32 byte line size");
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if ( descriptor[i] == 0x43)
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print_line(" L2 cache .......... 512 kb, 4-way associative, 32 byte line size");
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if ( descriptor[i] == 0x44)
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print_line(" L2 cache .......... 1 Mb, 4-way associative, 32 byte line size");
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if ( descriptor[i] == 0x45)
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print_line(" L2 cache .......... 2 Mb, 4-way associative, 32 byte line size");
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if ( descriptor[i] == 0x46)
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print_line(" L3 cache .......... 4 Mb, 4-way associative, 64 byte line size");
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if ( descriptor[i] == 0x47)
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print_line(" L3 cache .......... 8 Mb, 8-way associative, 64 byte line size");
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if ( descriptor[i] == 0x49)
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print_line(" L2 cache .......... 4 Mb, 16-way associative, 64 byte line size");
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if ( descriptor[i] == 0x50)
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print_line(" Instruction TLB ... 4 kb and 2 Mb or 4 Mb pages, 64 entries");
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if ( descriptor[i] == 0x51)
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print_line(" Instruction TLB ... 4 kb and 2 Mb or 4 Mb pages, 128 entries");
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if ( descriptor[i] == 0x52)
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print_line(" Instruction TLB ... 4 kb and 2 Mb or 4 Mb pages, 256 entries");
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if ( descriptor[i] == 0x56)
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print_line(" Data TLB .......... 4 Mb pages, 4-way associative, 16 entries");
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if ( descriptor[i] == 0x57)
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print_line(" Data TLB .......... 4 Kb pages, 4-way associative, 16 entries");
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if ( descriptor[i] == 0x5B)
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print_line(" Data TLB .......... 4 kb and 4 Mb pages, 64 entries");
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if ( descriptor[i] == 0x5C)
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print_line(" Data TLB .......... 4 kb and 4 Mb pages, 128 entries");
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if ( descriptor[i] == 0x5D)
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print_line(" Data TLB .......... 4 kb and 4 Mb pages, 256 entries");
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if ( descriptor[i] == 0x60)
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print_line(" L1 data cache ..... 16 kb, 8-way associative, 64 byte line size");
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if ( descriptor[i] == 0x66)
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print_line(" L1 data cache ..... 8 kb, 4-way associative, 64 byte line size");
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if ( descriptor[i] == 0x67)
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print_line(" L1 data cache ..... 16 kb, 4-way associative, 64 byte line size");
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if ( descriptor[i] == 0x68)
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print_line(" L1 data cache ..... 32 kb, 4-way associative, 64 byte line size");
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if ( descriptor[i] == 0x70)
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print_line(" Trace cache ...... 12k uop, 8-way associative");
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if ( descriptor[i] == 0x71)
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print_line(" Trace cache ...... 16k uop, 8-way associative");
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if ( descriptor[i] == 0x72)
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print_line(" Trace cache ...... 32k uop, 8-way associative");
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if ( descriptor[i] == 0x78)
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print_line(" L2 cache .......... 1 MB , 8-way associative, 64byte line size");
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if ( descriptor[i] == 0x79)
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print_line(" L2 cache .......... 128 kb, 8-way associative, sectored, 64 byte line size");
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if ( descriptor[i] == 0x7A)
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print_line(" L2 cache .......... 256 kb, 8-way associative, sectored, 64 byte line size");
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if ( descriptor[i] == 0x7B)
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print_line(" L2 cache .......... 512 kb, 8-way associative, sectored, 64 byte line size");
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if ( descriptor[i] == 0x7C)
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print_line(" L2 cache .......... 1M Byte, 8-way associative, sectored, 64 byte line size");
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if ( descriptor[i] == 0x7D)
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print_line(" L2 cache .......... 2M Byte, 8-way associative, 64 byte line size");
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if ( descriptor[i] == 0x7F)
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print_line(" L2 cache .........512K Byte, 2-way associative, 64 byte line size");
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if ( descriptor[i] == 0x82)
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print_line(" L2 cache .......... 256 kb, 8-way associative, 32 byte line size");
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if ( descriptor[i] == 0x83)
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print_line(" L2 cache .......... 512K Byte, 8-way associative, 32 byte line size");
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if ( descriptor[i] == 0x84)
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print_line(" L2 cache .......... 1 Mb, 8-way associative, 32 byte line size");
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if ( descriptor[i] == 0x85)
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print_line(" L2 cache .......... 2 Mb, 8-way associative, 32 byte line size");
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if ( descriptor[i] == 0x86)
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print_line(" L2 cache .......... 512K Byte, 4-way associative, 64 byte line size");
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if ( descriptor[i] == 0x87)
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print_line(" L2 cache .......... 1M Byte, 8-way associative, 64 byte line size");
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if ( descriptor[i] == 0xB0)
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print_line(" Instruction TLB 4K-Byte Pages, 4-way associative, 128 entries");
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if ( descriptor[i] == 0xB3)
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print_line(" Data TLB 4K-Byte Pages, 4-way associative, 128 entries");
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if ( descriptor[i] == 0xB4)
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print_line(" Data TLB 4K-Byte Pages, 4-way associative, 256 entries");
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if ( descriptor[i] == 0xF0)
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print_line(" 64-byte prefetching");
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if ( descriptor[i] == 0xF1)
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print_line(" 128-byte prefetching");
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}
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}
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void get_deterministic_cache_parameters(){
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uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
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native_cpuid(0, eax, ebx, ecx, edx);
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if(eax < 4){
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//Not supported on this processor
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return;
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}
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size_t caches = 0;
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while(caches < 1000){
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native_cpuid(4, eax, ebx, ecx, edx);
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if ( (eax & 0x1F) == 0 ) {
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// No more caches
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break;
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}
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if ((eax & 0x1F) == 1){
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print("Data Cache: ");
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}
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if ((eax & 0x1F) == 2){
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print("Instruction Cache: ");
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}
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if ((eax & 0x1F) == 3){
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print("Unified Cache: ");
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}
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printf( "Level %u: ", static_cast<size_t>((eax & 0xE0)/32));
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printf( "Max Threads %u: ", static_cast<size_t>(((eax & 0x03FFC000)/(8192))+1));
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printf( "Max Procs. %u: " , static_cast<size_t>(((eax & 0xFC000000)/(4*256*65536))+1));
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printf( "Line Size = %u: ", static_cast<size_t>((ebx & 0xFFF ) + 1));
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printf( "Associativity = %u: ", (static_cast<size_t>((ebx & 0xFFC00000)/4*16*65536) + 1));
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printf( "Sets = %u:\n", static_cast<size_t>(ecx + 1));
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++caches;
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}
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}
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} //end of anonymous namespace
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int main(){
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get_base_info();
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get_vendor_id();
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get_brand_string();
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get_features();
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get_cache_info();
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//get_deterministic_cache_parameters();
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exit(0);
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}
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