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32 lines
1006 B
V
32 lines
1006 B
V
// SSE Instruction Set
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// SSSE3: Added with Xeon 5100 and early Core 2
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// PSIGNW, PSIGND, PSIGNB, PSHUFB, PMULHRSW, PMADDUBSW, PHSUBW, PHSUBSW, PHSUBD, PHADDW, PHADDSW,
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// PHADDD, PALIGNR, PABSW, PABSD, PABSB
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// The PSIGNW instruction negates or leaves elements unchanged based on another vector's signs.
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@[if amd64 && !tinyc && !msvc]
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fn psignw_example(a &i16, b &i16, result &i16) {
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unsafe {
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asm volatile amd64 {
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movdqa xmm0, [a] // Load 8 signed 16-bit integers from array a into xmm0
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movdqa xmm1, [b] // Load 8 signed 16-bit integers from array b into xmm1
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psignw xmm0, xmm1 // Adjust the sign of elements in xmm0 based on xmm1
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movdqa [result], xmm0 // Store the result back to memory
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; ; r (a)
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r (b)
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r (result)
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; xmm0
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xmm1
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}
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}
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}
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fn main() {
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a0 := [i16(1), -2, 3, -4, 5, -6, 7, -8]
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b0 := [i16(1), -1, 1, -1, 1, -1, 1, -1]
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result0 := []i16{len: 8}
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psignw_example(&a0[0], &b0[0], &result0[0])
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dump(result0)
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assert result0 == [i16(1), 2, 3, 4, 5, 6, 7, 8]
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}
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