; Options for the MIPS port of the compiler
;
; Copyright (C) 2005, 2007, 2008, 2010, 2011 Free Software Foundation, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
; License for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3.  If not see
; <http://www.gnu.org/licenses/>.

m32
Target RejectNegative Mask(32BIT)
Generate RV32 code

m64
Target RejectNegative InverseMask(32BIT, 64BIT)
Generate RV64 code

mbranch-cost=
Target RejectNegative Joined UInteger Var(riscv_branch_cost)
-mbranch-cost=COST	Set the cost of branches to roughly COST instructions

mhard-float
Target Report RejectNegative InverseMask(SOFT_FLOAT_ABI, HARD_FLOAT_ABI)
Allow the use of hardware floating-point ABI and instructions

mmemcpy
Target Report Mask(MEMCPY)
Don't optimize block moves

mplt
Target Report Var(TARGET_PLT) Init(1)
When generating -fpic code, allow the use of PLTs. Ignored for fno-pic.

msoft-float
Target Report RejectNegative Mask(SOFT_FLOAT_ABI)
Prevent the use of all hardware floating-point instructions

mfdiv
Target Report RejectNegative Mask(FDIV)
Use hardware floating-point divide and square root instructions

march=
Target RejectNegative Joined Var(riscv_arch_string)
-march=			Generate code for given RISC-V ISA (e.g. RV64IM)

mtune=
Target RejectNegative Joined Var(riscv_tune_string)
-mtune=PROCESSOR	Optimize the output for PROCESSOR

msmall-data-limit=
Target Joined Separate UInteger Var(g_switch_value) Init(8)
-msmall-data-limit=<number>	Put global and static data smaller than <number> bytes into a special section (on some targets)

matomic
Target Report Mask(ATOMIC)
Use hardware atomic memory instructions.

mmuldiv
Target Report Mask(MULDIV)
Use hardware instructions for integer multiplication and division.

mlra
Target Report Var(riscv_lra_flag) Init(0) Save
Use LRA instead of reload

mcmodel=
Target RejectNegative Joined Var(riscv_cmodel_string)
Use given RISC-V code model (medlow or medany)