/* $NetBSD: dwc_mmc_reg.h,v 1.4 2015/01/17 19:32:50 jmcneill Exp $ */ /*- * Copyright (c) 2014 Jared D. McNeill * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #ifndef _DWC_MMC_REG_H #define _DWC_MMC_REG_H #define DWC_MMC_CTRL_REG 0x0000 #define DWC_MMC_PWREN_REG 0x0004 #define DWC_MMC_CLKDIV_REG 0x0008 #define DWC_MMC_CLKSRC_REG 0x000c #define DWC_MMC_CLKENA_REG 0x0010 #define DWC_MMC_TMOUT_REG 0x0014 #define DWC_MMC_CTYPE_REG 0x0018 #define DWC_MMC_BLKSIZ_REG 0x001c #define DWC_MMC_BYTCNT_REG 0x0020 #define DWC_MMC_INTMASK_REG 0x0024 #define DWC_MMC_CMDARG_REG 0x0028 #define DWC_MMC_CMD_REG 0x002c #define DWC_MMC_RESP0_REG 0x0030 #define DWC_MMC_RESP1_REG 0x0034 #define DWC_MMC_RESP2_REG 0x0038 #define DWC_MMC_RESP3_REG 0x003c #define DWC_MMC_MINTSTS_REG 0x0040 #define DWC_MMC_RINTSTS_REG 0x0044 #define DWC_MMC_STATUS_REG 0x0048 #define DWC_MMC_FIFOTH_REG 0x004c #define DWC_MMC_CDETECT_REG 0x0050 #define DWC_MMC_WRTPRT_REG 0x0054 #define DWC_MMC_TCBCNT_REG 0x005c #define DWC_MMC_TBBCNT_REG 0x0060 #define DWC_MMC_DEBNCE_REG 0x0064 #define DWC_MMC_USRID_REG 0x0068 #define DWC_MMC_VERID_REG 0x006c #define DWC_MMC_UHS_REG 0x0074 #define DWC_MMC_RST_REG 0x0078 #define DWC_MMC_CARDTHRCTL_REG 0x0100 #define DWC_MMC_BACK_END_POWER_REG 0x0104 #define DWC_MMC_FIFO_BASE_REG 0x0200 #define DWC_MMC_CTRL_ABORT_READ_DATA __BIT(8) #define DWC_MMC_CTRL_SEND_IRQ_RESPONSE __BIT(7) #define DWC_MMC_CTRL_READ_WAIT __BIT(6) #define DWC_MMC_CTRL_DMA_ENABLE __BIT(5) #define DWC_MMC_CTRL_INT_ENABLE __BIT(4) #define DWC_MMC_CTRL_DMA_RESET __BIT(2) #define DWC_MMC_CTRL_FIFO_RESET __BIT(1) #define DWC_MMC_CTRL_CONTROLLER_RESET __BIT(0) #define DWC_MMC_CTRL_RESET_ALL \ (DWC_MMC_CTRL_CONTROLLER_RESET | \ DWC_MMC_CTRL_FIFO_RESET | \ DWC_MMC_CTRL_DMA_RESET) #define DWC_MMC_PWREN_POWER_ENABLE __BIT(0) #define DWC_MMC_CLKDIV_CLK_DIVIDER0 __BITS(7,0) #define DWC_MMC_CLKENA_CCLK_LOW_POWER __BIT(16) #define DWC_MMC_CLKENA_CCLK_ENABLE __BIT(0) #define DWC_MMC_TMOUT_DATA_TIMEOUT __BITS(31,8) #define DWC_MMC_TMOUT_RESPONSE_TIMEOUT __BITS(7,0) #define DWC_MMC_CTYPE_CARD_WIDTH_8 __BIT(16) #define DWC_MMC_CTYPE_CARD_WIDTH_4 __BIT(0) #define DWC_MMC_CTYPE_CARD_WIDTH_1 0 #define DWC_MMC_INT_SDIO_INT __BIT(24) #define DWC_MMC_INT_NEW_INT __BIT(16) #define DWC_MMC_INT_MASK __BITS(15,0) #define DWC_MMC_INT_EBE __BIT(15) #define DWC_MMC_INT_ACD __BIT(14) #define DWC_MMC_INT_SBE __BIT(13) #define DWC_MMC_INT_HLE __BIT(12) #define DWC_MMC_INT_FRUN __BIT(11) #define DWC_MMC_INT_HTO __BIT(10) #define DWC_MMC_INT_DRTO __BIT(9) #define DWC_MMC_INT_RTO __BIT(8) #define DWC_MMC_INT_DCRC __BIT(7) #define DWC_MMC_INT_RCRC __BIT(6) #define DWC_MMC_INT_RXDR __BIT(5) #define DWC_MMC_INT_TXDR __BIT(4) #define DWC_MMC_INT_DTO __BIT(3) #define DWC_MMC_INT_CD __BIT(2) #define DWC_MMC_INT_RE __BIT(1) #define DWC_MMC_INT_CARDDET __BIT(0) #define DWC_MMC_INT_ERROR \ (DWC_MMC_INT_RE | DWC_MMC_INT_RCRC | DWC_MMC_INT_DCRC | \ DWC_MMC_INT_RTO | DWC_MMC_INT_DRTO | DWC_MMC_INT_HTO | \ DWC_MMC_INT_HLE | DWC_MMC_INT_SBE | DWC_MMC_INT_EBE) #define DWC_MMC_INT_BITS \ "\20" \ "\x19" "SDIO_INT" \ "\x11" "NEW_INT" \ "\x10" "EBE" \ "\x0f" "ACD" \ "\x0e" "SBE" \ "\x0d" "HLE" \ "\x0c" "FRUN" \ "\x0b" "HTO" \ "\x0a" "DRTO" \ "\x09" "RTO" \ "\x08" "DCRC" \ "\x07" "RCRC" \ "\x06" "RXDR" \ "\x05" "TXDR" \ "\x04" "DTO" \ "\x03" "CD" \ "\x02" "RE" \ "\x01" "CARDDET" #define DWC_MMC_CMD_START_CMD __BIT(31) #define DWC_MMC_CMD_USE_HOLD_REG __BIT(29) #define DWC_MMC_CMD_VOLT_SWITCH __BIT(28) #define DWC_MMC_CMD_BOOT_MODE __BIT(27) #define DWC_MMC_CMD_DISABLE_BOOT __BIT(26) #define DWC_MMC_CMD_EXPECT_BOOT_ACK __BIT(25) #define DWC_MMC_CMD_ENABLE_BOOT __BIT(24) #define DWC_MMC_CMD_UPDATE_CLOCK_REGS_ONLY __BIT(21) #define DWC_MMC_CMD_SEND_INIT __BIT(15) #define DWC_MMC_CMD_STOP_ABORT_CMD __BIT(14) #define DWC_MMC_CMD_WAIT_PRVDATA_COMPLETE __BIT(13) #define DWC_MMC_CMD_SEND_AUTO_STOP __BIT(12) #define DWC_MMC_CMD_TRANSFER_MODE __BIT(11) #define DWC_MMC_CMD_WR __BIT(10) #define DWC_MMC_CMD_DATA_EXPECTED __BIT(9) #define DWC_MMC_CMD_CHECK_RESP_CRC __BIT(8) #define DWC_MMC_CMD_RESP_LEN __BIT(7) #define DWC_MMC_CMD_RESP_EXPECTED __BIT(6) #define DWC_MMC_CMD_INDEX __BITS(5,0) #define DWC_MMC_STATUS_DMA_REQ __BIT(31) #define DWC_MMC_STATUS_DMA_ACK __BIT(30) #define DWC_MMC_STATUS_FIFO_COUNT __BITS(29,17) #define DWC_MMC_STATUS_RESP_INDEX __BITS(16,11) #define DWC_MMC_STATUS_DATA_STATE_MC_BUSY __BIT(10) #define DWC_MMC_STATUS_DATA_BUSY __BIT(9) #define DWC_MMC_STATUS_DATA_3_STATUS __BIT(8) #define DWC_MMC_STATUS_COMMAND_FSM_STATES __BITS(7,4) #define DWC_MMC_STATUS_FIFO_FULL __BIT(3) #define DWC_MMC_STATUS_FIFO_EMPTY __BIT(2) #define DWC_MMC_STATUS_FIFO_TX_WATERMARK __BIT(1) #define DWC_MMC_STATUS_FIFO_RX_WATERMARK __BIT(0) #define DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE __BITS(30,28) #define DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE_1 0 #define DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE_4 1 #define DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE_8 2 #define DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE_16 3 #define DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE_32 4 #define DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE_64 5 #define DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE_128 6 #define DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE_256 7 #define DWC_MMC_FIFOTH_RX_WMARK __BITS(27,16) #define DWC_MMC_FIFOTH_TX_WMARK __BITS(11,0) #define DWC_MMC_CDETECT_CARD_DETECT_N __BIT(0) #define DWC_MMC_WRTPRT_WRITE_PROTECT __BIT(0) #define DWC_MMC_DEBNCE_DEBOUNCE_COUNT __BITS(23,0) #define DWC_MMC_UHS_DDR __BIT(16) #define DWC_MMC_UHS_VOLT __BIT(0) #define DWC_MMC_RST_CARD_RESET __BIT(0) #define DWC_MMC_CARDTHRCTL_CARDRDTHRESHOLD __BITS(27,16) #define DWC_MMC_CARDTHRCTL_CARDRDTHREN __BIT(0) #define DWC_MMC_BACK_END_POWER_ENABLE __BIT(0) #endif /* !_DWC_MMC_REG_H */