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587 lines
19 KiB
C
587 lines
19 KiB
C
/* Definitions of target machine for GNU compiler, for CR16.
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Copyright (C) 2012-2013 Free Software Foundation, Inc.
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Contributed by KPIT Cummins Infosystems Limited.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published
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by the Free Software Foundation; either version 3, or (at your
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option) any later version.
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GCC is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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#ifndef GCC_CR16_H
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#define GCC_CR16_H
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#define OBJECT_FORMAT_ELF
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/* Controlling the driver. */
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/* The GNU C++ standard library requires that these macros be defined. */
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#undef CPLUSPLUS_CPP_SPEC
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#define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)"
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#undef STARTFILE_SPEC
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#define STARTFILE_SPEC "crt1.o%s crti.o%s crtbegin.o%s crtlibid.o%s"
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#undef ENDFILE_SPEC
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#define ENDFILE_SPEC "crtend.o%s crtn.o%s"
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#undef MATH_LIBRARY
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#define MATH_LIBRARY ""
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#undef LIB_SPEC
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#define LIB_SPEC "-( -lc %{msim*:-lsim}%{!msim*:-lnosys} -) \
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%{msim*:%{!T*:-Tsim.ld}} \
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%{!T*:%{!msim*: %{-Telf32cr16.x}}}"
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/* Run-time target specification. */
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#ifndef TARGET_CPU_CPP_BUILTINS
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#define TARGET_CPU_CPP_BUILTINS() \
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do \
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{ \
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builtin_define ("__CR__"); \
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builtin_define ("__CR16__"); \
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builtin_define ("__CR16C__"); \
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if (TARGET_CR16CP) \
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builtin_define ("__CR16CP__"); \
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else \
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builtin_define ("__CR16CSTD__"); \
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if (CR16_TARGET_DATA_NEAR) \
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builtin_define ("__DATA_NEAR__"); \
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if (CR16_TARGET_DATA_MEDIUM) \
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builtin_define ("__DATA_MEDIUM__"); \
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if (CR16_TARGET_DATA_FAR) \
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builtin_define ("__DATA_FAR__"); \
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if (TARGET_INT32) \
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builtin_define ("__INT32__"); \
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} \
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while (0)
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#endif
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/* Force the generation of dwarf .debug_frame sections even if not
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compiling -g. This guarantees that we can unwind the stack. */
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#define DWARF2_FRAME_INFO 1
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#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
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/* Generate .file/.loc directives, so that the assembler generates the
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line table. */
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#define DWARF2_ASM_LINE_DEBUG_INFO 1
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#define CR16_TARGET_DATA_NEAR cr16_is_data_model (DM_NEAR)
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#define CR16_TARGET_DATA_MEDIUM cr16_is_data_model (DM_DEFAULT)
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#define CR16_TARGET_DATA_FAR cr16_is_data_model (DM_FAR)
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/* Storage layout. */
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#define BITS_BIG_ENDIAN 0
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#define BYTES_BIG_ENDIAN 0
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#define WORDS_BIG_ENDIAN 0
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#define UNITS_PER_WORD 2
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/* Units per 32-bit (DWORD). */
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#define CR16_UNITS_PER_DWORD 4
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#define POINTER_SIZE 32
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#define PARM_BOUNDARY 16
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#define STACK_BOUNDARY (MAX (BIGGEST_ALIGNMENT, PARM_BOUNDARY))
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#define FUNCTION_BOUNDARY BIGGEST_ALIGNMENT
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/* Biggest alignment on CR16C+ is 32-bit as internal bus is AMBA based
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where as CR16C is proprietary internal bus architecture. */
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#define BIGGEST_ALIGNMENT ((TARGET_CR16CP) ? 32 : 16)
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#define MAX_FIXED_MODE_SIZE 64
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/* In CR16 arrays of chars are word-aligned, so strcpy () will be faster. */
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#define DATA_ALIGNMENT(TYPE, ALIGN) \
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(((TREE_CODE (TYPE) == ARRAY_TYPE) \
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&& (TYPE_MODE (TREE_TYPE (TYPE)) == QImode) \
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&& ((ALIGN) < BITS_PER_WORD)) \
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? (BITS_PER_WORD) : (ALIGN))
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/* In CR16 strings are word-aligne; strcpy from constants will be faster. */
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#define CONSTANT_ALIGNMENT(CONSTANT, ALIGN) \
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(((TREE_CODE (CONSTANT) == STRING_CST) && ((ALIGN) < BITS_PER_WORD)) \
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? (BITS_PER_WORD) : (ALIGN))
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#define STRICT_ALIGNMENT 0
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#define PCC_BITFIELD_TYPE_MATTERS 1
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/* Layout of source language data types. */
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#define INT_TYPE_SIZE (TARGET_INT32 ? 32 : 16)
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#define SHORT_TYPE_SIZE 16
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#define LONG_TYPE_SIZE 32
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#define LONG_LONG_TYPE_SIZE 64
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#define FLOAT_TYPE_SIZE 32
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#define DOUBLE_TYPE_SIZE 64
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#define LONG_DOUBLE_TYPE_SIZE 64
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#define DEFAULT_SIGNED_CHAR 1
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#define SIZE_TYPE "long unsigned int"
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#define PTRDIFF_TYPE "long int"
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#define WCHAR_TYPE "short unsigned int"
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#define WCHAR_TYPE_SIZE 16
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/* By default, the C++ compiler will use the lowest bit of the pointer
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to function to indicate a pointer-to-member-function points to a
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virtual member function. However, in CR architecture FUNCTION_BOUNDARY
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indicates function addresses are always even, but function pointers can be
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odd (after right-shifting them when loading them into a register), and the
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default doesn't work. In that case, the lowest bit of the delta
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field will be used (the remainder of the field is shifted to the left). */
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#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
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/* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
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values must be in memory. */
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#define DEFAULT_PCC_STRUCT_RETURN 0
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/* Register usage. */
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/* First 32-bit register is R12. */
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#define CR16_FIRST_DWORD_REGISTER 12
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#define FIRST_PSEUDO_REGISTER 16
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/* 1 for registers that have pervasive standard uses
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and are not available for the register allocator.
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On the CR16, only the stack pointer (r15) is such. */
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#define FIXED_REGISTERS \
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{ \
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/* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10. */ \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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/* r11 r12 r13 ra sp. */ \
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0, 0, 0, 0, 1 \
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}
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/* 1 for registers not available across function calls.
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These must include the FIXED_REGISTERS and also any
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registers that can be used without being saved.
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The latter must include the registers where values are returned
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and the register where structure-value addresses are passed.
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On the CR16, calls clobbers r0-r6 (scratch registers),
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ra (the return address) and sp (the stack pointer). */
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#define CALL_USED_REGISTERS \
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{ \
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/* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10. */ \
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1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
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/* r11 r12 r13 ra sp. */ \
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0, 0, 0, 1, 1 \
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}
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/* Returns 1 if the register is longer than word size, 0 otherwise. */
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#define LONG_REG_P(REGNO) \
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(HARD_REGNO_NREGS (REGNO, \
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GET_MODE_WIDER_MODE (smallest_mode_for_size \
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(BITS_PER_WORD, MODE_INT))) == 1)
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#define HARD_REGNO_NREGS(REGNO, MODE) \
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((REGNO >= CR16_FIRST_DWORD_REGISTER) \
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? ((GET_MODE_SIZE (MODE) + CR16_UNITS_PER_DWORD - 1) / CR16_UNITS_PER_DWORD)\
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: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
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/* Nonzero if it is permissible to store a value of mode @var{mode} in hard
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register number @var{regno} (or in several registers starting with that
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one). On the CR16 architecture, all registers can hold all modes,
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except that double precision floats (and double ints) must fall on
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even-register boundaries. */
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#define HARD_REGNO_MODE_OK(REGNO, MODE) cr16_hard_regno_mode_ok (REGNO, MODE)
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#define NOTICE_UPDATE_CC(EXP, INSN) \
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notice_update_cc ((EXP))
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/* Interrupt functions can only use registers that have already been
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saved by the prologue, even if they would normally be call-clobbered
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Check if sizes are same and then check if it is possible to rename. */
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#define HARD_REGNO_RENAME_OK(SRC, DEST) \
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(!cr16_interrupt_function_p () || (df_regs_ever_live_p (DEST)))
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/* Exception handling stuff. */
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/*To ensure correct dwarf unwinding. */
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#define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((optimize ("no-gcse","no-dse")))
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#define gen_rtx_RA gen_rtx_REG (Pmode, RETURN_ADDRESS_REGNUM)
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/* Use (r8,r7) and (r10,r9) to pass exception handling information. */
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#define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? (N*2 + 7) : INVALID_REGNUM)
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#define DWARF2_UNWIND_INFO 1
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/* (r5,r4) holds a stack adjustment for returning to a handler. */
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#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 4)
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#define EH_RETURN_HANDLER_RTX \
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gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, -4))
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#define INCOMING_RETURN_ADDR_RTX gen_rtx_RA
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#define DWARF_FRAME_RETURN_COLUMN \
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DWARF_FRAME_REGNUM (RETURN_ADDRESS_REGNUM)
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#define INCOMING_FRAME_SP_OFFSET 0
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#define FRAME_POINTER_CFA_OFFSET(FNDECL) 0
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/* A C expression whose value is RTL representing the value of the return
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address for the frame COUNT steps up from the current frame. */
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#define RETURN_ADDR_RTX(COUNT, FRAME) \
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(0 == COUNT) ? gen_rtx_PLUS (Pmode, gen_rtx_RA, gen_rtx_RA) \
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: const0_rtx
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#define MODES_TIEABLE_P(MODE1, MODE2) \
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(GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
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enum reg_class
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{
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NO_REGS,
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SHORT_REGS,
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LONG_REGS,
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NOSP_REGS,
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DOUBLE_BASE_REGS,
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GENERAL_REGS,
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ALL_REGS,
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LIM_REG_CLASSES
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};
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#define N_REG_CLASSES (int) LIM_REG_CLASSES
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#define REG_CLASS_NAMES \
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{ \
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"NO_REGS", \
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"SHORT_REGS", \
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"LONG_REGS", \
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"NOSP_REGS", \
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"DOUBLE_BASE_REGS", \
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"GENERAL_REGS", \
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"ALL_REGS" \
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}
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#define REG_CLASS_CONTENTS \
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{ \
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{0x00000000}, /* NO_REGS */ \
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{0x00000FFF}, /* SHORT_REGS : 0 - 11 */ \
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{0x0000F000}, /* LONG_REGS : 12 - 15 */ \
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{0x00007FFF}, /* NOSP_REGS : 0 - 14 */ \
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{0x0000F555}, /* DOUBLE_BASE_REGS : 2,4,6,8,10 */ \
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{0x0000FFFF}, /* GENERAL_REGS : 0 - 15 */ \
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{0x0000FFFF} /* ALL_REGS : 0 - 15 */ \
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}
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#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
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#define REGNO_REG_CLASS(REGNO) cr16_regno_reg_class (REGNO)
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#define BASE_REG_CLASS GENERAL_REGS
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#define MODE_BASE_REG_CLASS(MODE) \
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(GET_MODE_SIZE (MODE) <= 4 ? (BASE_REG_CLASS) : (DOUBLE_BASE_REGS))
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#define INDEX_REG_CLASS LONG_REGS
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#define CR16_REGNO_OK_FOR_BASE_P(REGNO) \
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(((REGNO) < FIRST_PSEUDO_REGISTER) \
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|| (reg_renumber && ((unsigned) reg_renumber[REGNO] \
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< FIRST_PSEUDO_REGISTER)))
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/* Use even-numbered reg for 64-bit accesses. */
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#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
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(CR16_REGNO_OK_FOR_BASE_P(REGNO) && \
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((GET_MODE_SIZE (MODE) > 4 && \
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(REGNO) < CR16_FIRST_DWORD_REGISTER) \
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? (0 == ((REGNO) & 1)) \
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: 1))
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/* TODO: For now lets not support index addressing mode. */
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#define REGNO_OK_FOR_INDEX_P(REGNO) \
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(((REGNO >= CR16_FIRST_DWORD_REGISTER) \
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&& ((REGNO) < FIRST_PSEUDO_REGISTER)) \
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|| (reg_renumber \
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&& (((unsigned) reg_renumber[REGNO] >= CR16_FIRST_DWORD_REGISTER) \
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&& ((unsigned) reg_renumber[REGNO] < FIRST_PSEUDO_REGISTER))) \
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)
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#define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS
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/* The maximum number of consecutive registers of class CLASS needed to
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hold a value of mode MODE.
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On the CompactRISC architecture, the size of MODE in words.
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The size of MODE in double words for the class LONG_REGS.
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The following check assumes if the class is not LONG_REGS, then
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all (NO_REGS, SHORT_REGS, NOSP_REGS and GENERAL_REGS) other classes are
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short. We may have to check if this can cause any degradation in
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performance. */
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#define CLASS_MAX_NREGS(CLASS, MODE) \
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(CLASS == LONG_REGS \
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? (GET_MODE_SIZE (MODE) + CR16_UNITS_PER_DWORD - 1) / CR16_UNITS_PER_DWORD\
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: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
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/* Macros to check the range of integers . These macros were used across
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the port, majorly in constraints.md, predicates.md files. */
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#define SIGNED_INT_FITS_N_BITS(imm, N) \
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((((imm) < ((HOST_WIDE_INT) 1 << ((N) - 1))) \
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&& ((imm) >= -((HOST_WIDE_INT) 1 << ((N) - 1)))) ? 1 : 0)
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#define UNSIGNED_INT_FITS_N_BITS(imm, N) \
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(((imm) < ((HOST_WIDE_INT) 1 << (N)) && (imm) >= (HOST_WIDE_INT) 0) ? 1 : 0)
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#define IN_RANGE_P(VALUE, LOW, HIGH) \
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((((HOST_WIDE_INT)(VALUE)) >= (HOST_WIDE_INT)(LOW)) \
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&& (((HOST_WIDE_INT)(VALUE)) <= ((HOST_WIDE_INT)(HIGH))))
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#define IN_RAN(VALUE, LOW, HIGH) \
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(((((HOST_WIDE_INT)(VALUE)) >= (HOST_WIDE_INT)(LOW)) \
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&& (((HOST_WIDE_INT)(VALUE)) <= ((HOST_WIDE_INT)(HIGH)))) ? 1 : 0)
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/* This check is for sbit/cbit instruction. */
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#define OK_FOR_Z(OP) \
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((GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == CONST_INT) \
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|| (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG) \
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|| (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == PLUS \
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&& GET_CODE (XEXP ((XEXP (OP, 0)), 0)) == REG \
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&& GET_CODE (XEXP ((XEXP (OP, 0)), 1)) == CONST_INT))
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/* Stack layout and calling conventions. */
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#define STACK_GROWS_DOWNWARD
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#define STARTING_FRAME_OFFSET 0
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#define STACK_POINTER_REGNUM 15
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#define FRAME_POINTER_REGNUM 13
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#define ARG_POINTER_REGNUM 12
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#define STATIC_CHAIN_REGNUM 1
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#define RETURN_ADDRESS_REGNUM 14
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#define FIRST_PARM_OFFSET(FNDECL) 0
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#define ELIMINABLE_REGS \
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{ \
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{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
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{ ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
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{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM} \
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}
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#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
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do \
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{ \
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(OFFSET) = cr16_initial_elimination_offset ((FROM), (TO)); \
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} \
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while (0)
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/* Passing function arguments. */
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#define ACCUMULATE_OUTGOING_ARGS 0
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#define PUSH_ARGS 1
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#define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1)
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#ifndef CUMULATIVE_ARGS
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struct cumulative_args
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{
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int ints;
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int last_parm_in_reg;
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};
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#define CUMULATIVE_ARGS struct cumulative_args
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#endif
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/* On the CR16 architecture, Varargs routines should receive their parameters
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on the stack. */
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#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
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cr16_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME))
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#define FUNCTION_ARG_REGNO_P(REGNO) cr16_function_arg_regno_p (REGNO)
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/* Generating code for profiling - NOT IMPLEMENTED. */
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#undef FUNCTION_PROFILER
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#define FUNCTION_PROFILER(STREAM, LABELNO) \
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{ \
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sorry ("profiler support for CR16"); \
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}
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/* Trampolines for nested functions - NOT SUPPORTED. */
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#define TRAMPOLINE_SIZE 16
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/* ADDRESSING MODES. */
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#define CONSTANT_ADDRESS_P(X) \
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(GET_CODE (X) == LABEL_REF \
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|| GET_CODE (X) == SYMBOL_REF \
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|| GET_CODE (X) == CONST \
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|| GET_CODE (X) == CONST_INT)
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#define MAX_REGS_PER_ADDRESS 2
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#define HAVE_POST_INCREMENT 0
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#define HAVE_POST_DECREMENT 0
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#define HAVE_POST_MODIFY_DISP 0
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#define HAVE_POST_MODIFY_REG 0
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#ifdef REG_OK_STRICT
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#define CR16_REG_OK_FOR_BASE_P(X) CR16_REGNO_OK_FOR_BASE_P (REGNO (X))
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#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
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REGNO_MODE_OK_FOR_BASE_P (REGNO(X), MODE)
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#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
|
|
#else /* not REG_OK_STRICT. */
|
|
#define CR16_REG_OK_FOR_BASE_P(X) 1
|
|
#define REG_MODE_OK_FOR_BASE_P(X, MODE) 1
|
|
#define REG_OK_FOR_INDEX_P(X) 1
|
|
#endif /* not REG_OK_STRICT. */
|
|
|
|
/* Assume best case (branch predicted). */
|
|
#define BRANCH_COST(speed_p, predictable_p) 2
|
|
|
|
#define SLOW_BYTE_ACCESS 1
|
|
|
|
/* It is as good or better to call a constant function address than to
|
|
call an address kept in a register. */
|
|
#define NO_FUNCTION_CSE
|
|
|
|
/* Dividing the output into sections. */
|
|
|
|
#define TEXT_SECTION_ASM_OP "\t.section\t.text"
|
|
|
|
#define DATA_SECTION_ASM_OP "\t.section\t.data"
|
|
|
|
#define BSS_SECTION_ASM_OP "\t.section\t.bss"
|
|
|
|
/* Position independent code (PIC). */
|
|
/* NEAR_PIC for -fpic option. */
|
|
|
|
#define NEAR_PIC 1
|
|
|
|
/* FAR_PIC for -fPIC option. */
|
|
|
|
#define FAR_PIC 2
|
|
|
|
#define PIC_OFFSET_TABLE_REGNUM 12
|
|
|
|
#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
|
|
|
|
/* Assembler format. */
|
|
|
|
/* Character to start a comment. */
|
|
#define ASM_COMMENT_START "#"
|
|
|
|
#define GLOBAL_ASM_OP "\t.globl\t"
|
|
|
|
#undef USER_LABEL_PREFIX
|
|
#define USER_LABEL_PREFIX "_"
|
|
|
|
#undef ASM_OUTPUT_LABELREF
|
|
#define ASM_OUTPUT_LABELREF(STREAM, NAME) \
|
|
asm_fprintf (STREAM, "%U%s", (*targetm.strip_name_encoding) (NAME));
|
|
|
|
#define ASM_OUTPUT_SYMBOL_REF(STREAM, SYMBOL) \
|
|
do \
|
|
{ \
|
|
const char *rn = XSTR (SYMBOL, 0); \
|
|
assemble_name (STREAM, rn); \
|
|
if (SYMBOL_REF_FUNCTION_P (SYMBOL)) \
|
|
{ \
|
|
fprintf ((STREAM), "@c"); \
|
|
} \
|
|
} \
|
|
while (0)
|
|
|
|
#undef ASM_APP_ON
|
|
#define ASM_APP_ON "#APP\n"
|
|
|
|
#undef ASM_APP_OFF
|
|
#define ASM_APP_OFF "#NO_APP\n"
|
|
|
|
/* Switch into a generic section. */
|
|
#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
|
|
|
|
#undef INIT_SECTION_ASM_OP
|
|
#define INIT_SECTION_ASM_OP "\t.section\t.init"
|
|
|
|
#undef FINI_SECTION_ASM_OP
|
|
#define FINI_SECTION_ASM_OP "\t.section\t.fini"
|
|
|
|
/* Instruction output. */
|
|
|
|
#define REGISTER_NAMES \
|
|
{ \
|
|
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
|
|
"r8", "r9", "r10", "r11", "r12", "r13", "ra", "sp" \
|
|
}
|
|
|
|
/* Output of dispatch tables. */
|
|
|
|
/* Revisit. No PC relative case as label expressions are not
|
|
properly supported in binutils else we could have done this:
|
|
#define CASE_VECTOR_PC_RELATIVE (optimize_size ? 1 : 0). */
|
|
#define CASE_VECTOR_PC_RELATIVE 0
|
|
|
|
#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
|
|
((GET_MODE (BODY) == QImode) \
|
|
? fprintf ((FILE), "\t.byte (.L%d-.L%d) >> 1\n", \
|
|
VALUE, REL) \
|
|
: fprintf ((FILE), "\t.word (.L%d-.L%d) >> 1\n", \
|
|
VALUE, REL))
|
|
|
|
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
|
|
asm_fprintf ((STREAM), "\t.long\t.L%d@c\n", (VALUE))
|
|
|
|
/* Alignment in assembler file. */
|
|
|
|
#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
|
|
asm_fprintf ((STREAM), "\t.align\t%d\n", 1 << (POWER))
|
|
|
|
/* Miscellaneous parameters. */
|
|
|
|
#define CASE_VECTOR_MODE Pmode
|
|
|
|
#define MOVE_MAX 4
|
|
|
|
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
|
|
|
|
#define STORE_FLAG_VALUE 1
|
|
|
|
#define Pmode SImode
|
|
|
|
#define FUNCTION_MODE QImode
|
|
|
|
/* Define this boolean macro(s) to indicate whether or not your architecture
|
|
has (un)conditional branches that can span all of memory. It is used in
|
|
conjunction with an optimization that partitions hot and cold basic blocks
|
|
into separate sections of the executable.
|
|
CR16 contains branch instructions that span whole address space. */
|
|
#define HAS_LONG_COND_BRANCH 1
|
|
#define HAS_LONG_UNCOND_BRANCH 1
|
|
|
|
#endif /* End of GCC_CR16_H. */
|