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97 lines
3.5 KiB
C
97 lines
3.5 KiB
C
/* Definition of RISC-V target for GNU compiler.
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Copyright (C) 2011-2014 Free Software Foundation, Inc.
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Contributed by Andrew Waterman (waterman@cs.berkeley.edu) at UC Berkeley.
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Based on MIPS target for GNU compiler.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GCC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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#ifndef GCC_RISCV_PROTOS_H
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#define GCC_RISCV_PROTOS_H
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enum riscv_symbol_type {
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SYMBOL_ABSOLUTE,
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SYMBOL_GOT_DISP,
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SYMBOL_TLS,
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SYMBOL_TLS_LE,
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SYMBOL_TLS_IE,
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SYMBOL_TLS_GD
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};
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#define NUM_SYMBOL_TYPES (SYMBOL_TLS_GD + 1)
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enum riscv_code_model {
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CM_MEDLOW,
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CM_MEDANY,
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CM_PIC
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};
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extern enum riscv_code_model riscv_cmodel;
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extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
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extern int riscv_regno_mode_ok_for_base_p (int, enum machine_mode, bool);
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extern int riscv_address_insns (rtx, enum machine_mode, bool);
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extern int riscv_const_insns (rtx);
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extern int riscv_split_const_insns (rtx);
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extern int riscv_load_store_insns (rtx, rtx);
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extern rtx riscv_emit_move (rtx, rtx);
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extern bool riscv_split_symbol (rtx, rtx, enum machine_mode, rtx *);
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extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type);
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extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT);
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extern bool riscv_legitimize_move (enum machine_mode, rtx, rtx);
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extern bool riscv_legitimize_vector_move (enum machine_mode, rtx, rtx);
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extern rtx riscv_subword (rtx, bool);
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extern bool riscv_split_64bit_move_p (rtx, rtx);
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extern void riscv_split_doubleword_move (rtx, rtx);
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extern const char *riscv_output_move (rtx, rtx);
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extern const char *riscv_riscv_output_vector_move (enum machine_mode, rtx, rtx);
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#ifdef RTX_CODE
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extern void riscv_expand_scc (rtx *);
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extern void riscv_expand_conditional_branch (rtx *);
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#endif
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extern rtx riscv_expand_call (bool, rtx, rtx, rtx);
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extern void riscv_expand_fcc_reload (rtx, rtx, rtx);
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extern void riscv_set_return_address (rtx, rtx);
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extern bool riscv_expand_block_move (rtx, rtx, rtx);
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extern void riscv_expand_synci_loop (rtx, rtx);
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extern bool riscv_expand_ext_as_unaligned_load (rtx, rtx, HOST_WIDE_INT,
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HOST_WIDE_INT);
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extern bool riscv_expand_ins_as_unaligned_store (rtx, rtx, HOST_WIDE_INT,
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HOST_WIDE_INT);
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extern void riscv_order_regs_for_local_alloc (void);
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extern rtx riscv_return_addr (int, rtx);
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extern HOST_WIDE_INT riscv_initial_elimination_offset (int, int);
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extern void riscv_expand_prologue (void);
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extern void riscv_expand_epilogue (bool);
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extern bool riscv_can_use_return_insn (void);
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extern rtx riscv_function_value (const_tree, const_tree, enum machine_mode);
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extern enum reg_class riscv_secondary_reload_class (enum reg_class,
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enum machine_mode,
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rtx, bool);
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extern int riscv_class_max_nregs (enum reg_class, enum machine_mode);
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extern unsigned int riscv_hard_regno_nregs (int, enum machine_mode);
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extern void irix_asm_output_align (FILE *, unsigned);
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extern const char *current_section_name (void);
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extern unsigned int current_section_flags (void);
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extern void riscv_expand_vector_init (rtx, rtx);
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#endif /* ! GCC_RISCV_PROTOS_H */
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