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281 lines
7.3 KiB
ArmAsm
281 lines
7.3 KiB
ArmAsm
/* $NetBSD: acpi_wakecode.S,v 1.12 2014/01/15 22:24:41 joerg Exp $ */
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/*-
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* Copyright (c) 2007 Joerg Sonnenberger <joerg@netbsd.org>
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*
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* Copyright (c) 2002 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Takuya SHIOZAKI.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* This code is derived from FreeBSD. Original copyrights:
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*
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* Copyright (c) 2001 Takanori Watanabe <takawata@jp.freebsd.org>
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* Copyright (c) 2001 Mitsuru IWASAKI <iwasaki@jp.freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* FreeBSD: src/sys/i386/acpica/acpi_wakecode.S,v 1.1 2001/07/20 06:07:31 takawata Exp
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*/
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#define _LOCORE
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#include <machine/psl.h>
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#include <machine/segments.h>
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#include <machine/specialreg.h>
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#define ACPI_WAKEUP_ADDR 0x3000
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.text
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.code16
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.org 0 /* ACPI spec says: cs==(phys>>8), ip==(phys&0x000F) */
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.globl wakeup_16
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wakeup_16:
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nop
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cli
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cld
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/* Set up segment registers for real mode */
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movw %cs,%ax
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movw %ax,%ds
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movw %ax,%ss
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/* Small call stack */
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mov $0x1000,%sp
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/* Clear flags */
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pushl $0
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popfl
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/* Only beep on reset if machdep.acpi_beep_on_reset=1 */
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cmpb $1,WAKEUP_beep_on_reset
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jne 1f
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movb $0xc0,%al
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outb %al,$0x42
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movb $0x04,%al
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outb %al,$0x42
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inb $0x61,%al
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orb $0x3,%al
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outb %al,$0x61
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1:
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/* Only reset the VBIOS if machdep.acpi_vbios_reset=1 */
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cmpb $1,WAKEUP_vbios_reset
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jne 1f
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/* Kick the VBIOS. */
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lcall $0xc000,$3
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/* Reset registers in case the VBIOS changed them. */
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movw %cs,%ax
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movw %ax,%ds
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movw %ax,%ss
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/* If we need to restore a VESA VBE mode, do it now */
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cmpb $0,WAKEUP_vesa_modenum
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je 1f
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movw WAKEUP_vesa_modenum,%bx
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orw $0x4000,%bx
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movw $0x4f02,%ax
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int $0x10
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movw %cs,%ax
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movw %ax,%ds
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movw %ax,%ss
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1:
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/* Disable beep again if machdep.acpi_beep_on_reset=1 */
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cmpb $1,WAKEUP_beep_on_reset
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jne 1f
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inb $0x61,%al
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andb $0xfc,%al
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outb %al,$0x61
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1:
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/* Load temporary 32bit GDT */
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#ifdef __clang__
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lgdt tmp_gdt
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#else
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data32 addr32 lgdt tmp_gdt
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#endif
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/* Enable protected mode w/o paging */
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mov %cr0,%eax
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orl $(CR0_PE),%eax
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mov %eax,%cr0
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wakeup_sw32:
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/*
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* Switch to protected mode by intersegmental jump.
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* Target and everything else has to compensate for the new origin
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* as this is using the flat memory model now.
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*/
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ljmpl $0x8,$wakeup_32 + ACPI_WAKEUP_ADDR
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.code32
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.align 16
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wakeup_32:
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/*
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* Switched to protected mode w/o paging
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*/
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nop
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/* Set up segment registers and initial stack for protected mode */
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movw $0x10, %ax
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movw %ax,%ds
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movw %ax,%ss
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movl $(ACPI_WAKEUP_ADDR + 4096),%esp
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/* First, reset the PSL. */
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pushl $PSL_MBO
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popfl
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/* Enable PAE and potentially PSE */
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movl $(CR4_PAE|CR4_OSFXSR|CR4_OSXMMEXCPT|CR4_PSE),%eax
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movl %eax,%cr4
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/*
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* First switch to Long Mode. Do not restore the original
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* MSR EFER value directly, as enabling the NX bit without
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* paging will result in a GPF on AMD CPUs.
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*
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* Load the correct MSR EFER value now to not depend on the
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* data segment register directly after switching to Long Mode.
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* After this point, no instruction is allowed to clobber %ebx.
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*/
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movl WAKEUP_efer + ACPI_WAKEUP_ADDR,%ebx
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movl $MSR_EFER,%ecx
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rdmsr
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orl $EFER_LME, %eax
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wrmsr
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/* Load temporary PML4, code will switch to full PML4 later */
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movl WAKEUP_r_cr3 + ACPI_WAKEUP_ADDR,%eax
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movl %eax,%cr3
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/* Enable paging */
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movl %cr0,%eax
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orl $(CR0_PE|CR0_PG|CR0_NE|CR0_TS|CR0_MP|CR0_WP|CR0_AM),%eax
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movl %eax,%cr0
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/* Flush prefetch queue */
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jmp 1f
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1:
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/* Switch to temporary 64bit GDT */
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lgdt tmp_gdt64 + ACPI_WAKEUP_ADDR
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/* Switch to long mode using intersegmental jump. */
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ljmp $0x8, $wakeup_64 + ACPI_WAKEUP_ADDR
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.code64
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wakeup_64:
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/*
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* Load the normal system value of MSR EFER. This includes
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* enabling the SYSCALL extension and NXE (if supported).
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*/
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movl %ebx, %eax
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movl $MSR_EFER,%ecx
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wrmsr
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/* Reload data segment with default value */
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movw $GSEL(GDATA_SEL, SEL_KPL),%ax
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movw %ax,%ds
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movq WAKEUP_curcpu + ACPI_WAKEUP_ADDR,%r8
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movq WAKEUP_restorecpu + ACPI_WAKEUP_ADDR,%rbx
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/* Continue with wakeup in the high-level wakeup code */
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jmp *%rbx
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.align 8
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tmp_gdt:
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.word 0xffff
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.long tmp_gdtable + ACPI_WAKEUP_ADDR
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.align 8, 0
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tmp_gdtable:
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/* null */
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.word 0, 0
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.byte 0, 0, 0, 0
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/* code */
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.word 0xffff, 0
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.byte 0, 0x9f, 0xcf, 0
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/* data */
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.word 0xffff, 0
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.byte 0, 0x93, 0xcf, 0
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tmp_gdt64:
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.word 0xffff
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.long tmp_gdtable64 + ACPI_WAKEUP_ADDR
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tmp_gdtable64:
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.quad 0x0000000000000000
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.quad 0x00af9a000000ffff
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.quad 0x00cf92000000ffff
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.align 16, 0
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.global WAKEUP_r_cr3
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WAKEUP_r_cr3: .quad 0
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.global WAKEUP_restorecpu
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WAKEUP_restorecpu: .quad 0
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.global WAKEUP_vbios_reset
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WAKEUP_vbios_reset: .byte 0
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.global WAKEUP_vesa_modenum
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WAKEUP_vesa_modenum: .word 0
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.global WAKEUP_beep_on_reset
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WAKEUP_beep_on_reset: .byte 0
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.global WAKEUP_curcpu
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WAKEUP_curcpu: .quad 0
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.global WAKEUP_efer
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WAKEUP_efer: .long 0
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