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88 lines
3.5 KiB
C
88 lines
3.5 KiB
C
/* $NetBSD: p5pbreg.h,v 1.7 2012/07/11 17:13:31 rkujawa Exp $ */
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/*-
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* Copyright (c) 2011, 2012 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Radoslaw Kujawa.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Reverse engineered Phase5 PCI bridge memory map (firmware 44.71):
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*
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* 0xFFFA0000 - PCI register space, 64KB
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* 0xFFFC0000 - PCI configuration mechanism #1 data, 128KB
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* 0xFFFE0000 - (unknown, probably PCI bridge configuration registers, 4KB)
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*
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* 0xE0000000 - Permedia RAM on CVPPC/BVPPC (1st aperture), 8MB
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* 0xE0800000 - Permedia RAM on CVPPC/BVPPC (2nd aperture), 8MB
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* 0xE1000000 - Permedia registers on CVPPC/BVPPC, 128KB
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*
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* 0x80000000 - PCI cards memory space on G-REX, variable size
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*
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* Note: this map may not look the same for every firmware revision.
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*
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* The bridge is certainly capable of DMA, but this needs further reverse
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* engineering.
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*/
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#ifndef _AMIGA_P5PBREG_H_
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#define P5BUS_PCI_CONF_BASE 0xFFFC0000
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#define P5BUS_PCI_CONF_SIZE 0x00020000 /* up to 128kB */
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#define OFF_PCI_CONF_DATA 0x00000000 /* also 0 on CVPPC */
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#define OFF_PCI_DEVICE 0x00001000
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#define OFF_PCI_FUNCTION 0x00000100
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#define P5BUS_PCI_IO_BASE 0xFFFA0000
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#define P5BUS_PCI_IO_SIZE 0x00010000 /* 64kB */
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/* Bridge configuration */
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#define P5BUS_BRIDGE_BASE 0xFFFE0000
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#define P5BUS_BRIDGE_SIZE 0x00001000 /* 64kB, 4kB on some fw revs */
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#define OFF_BRIDGE_ENDIAN 0x0000 /* PCI_BRIDGE_BASE + offset */
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#define P5BUS_BRIDGE_ENDIAN_BIG 0x02 /* to switch into BE mode */
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#define OFF_BRIDGE_INTR 0x0010 /* ? XXX interrupt enable? */
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#define P5BUS_BRIDGE_INTR_INT2 0x01 /* ? XXX INT2? */
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/* CVPPC/BVPPC defaults. */
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#define P5BUS_PCI_MEM_BASE 0xE0000000
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/* #define P5BUS_PCI_MEM_BASE 0x80000000 */ /* default on G-REX */
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#define P5BUS_PCI_MEM_SIZE 0x01020000
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/* typical configuration of Permedia 2 on CVPPC/BVPPC */
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#define OFF_P2_APERTURE_1 0x0
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#define OFF_P2_APERTURE_2 0x00800000
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#define OFF_P2_REGS 0x01000000
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/* #define OFF_P2_REGS 0x0F000000 */ /* ? alt. Permedia regs */
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/* Permedia 2 vendor and product IDs, for CVPPC/BVPPC probe. */
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#define P5PB_PM2_VENDOR_ID 0x104C
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#define P5PB_PM2_PRODUCT_ID 0x3D07
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#endif /* _AMIGA_P5PBREG_H_ */
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