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277 lines
8.1 KiB
C
277 lines
8.1 KiB
C
/*-
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* Copyright (c) 2013, 2014 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry and Martin Husemann.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "locators.h"
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#include "axp806pm.h"
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#include "axp809pm.h"
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#include <sys/cdefs.h>
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__KERNEL_RCSID(1, "$NetBSD: awin_gige.c,v 1.22 2015/03/15 13:15:26 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <sys/intr.h>
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#include <sys/systm.h>
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#include <arm/allwinner/awin_reg.h>
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#include <arm/allwinner/awin_var.h>
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#if NAXP806PM > 0
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#include <dev/i2c/axp806.h>
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#endif
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#if NAXP809PM > 0
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#include <dev/i2c/axp809.h>
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#endif
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#include <net/if.h>
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#include <net/if_ether.h>
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#include <net/if_media.h>
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#include <dev/mii/miivar.h>
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#include <dev/ic/dwc_gmac_var.h>
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#include <dev/ic/dwc_gmac_reg.h>
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static int awin_gige_match(device_t, cfdata_t, void *);
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static void awin_gige_attach(device_t, device_t, void *);
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static void awin_gige_pmu_init(device_t);
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static int awin_gige_intr(void*);
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struct awin_gige_softc {
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struct dwc_gmac_softc sc_core;
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void *sc_ih;
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struct awin_gpio_pindata sc_power_pin;
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};
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static const struct awin_gpio_pinset awin_gige_gpio_pinset = {
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'A', AWIN_PIO_PA_GMAC_FUNC, AWIN_PIO_PA_GMAC_PINS,
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};
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static const struct awin_gpio_pinset awin_gige_gpio_pinset_a31 = {
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'A', AWIN_A31_PIO_PA_GMAC_FUNC, AWIN_A31_PIO_PA_GMAC_PINS, 0, 3
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};
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static const struct awin_gpio_pinset awin_gige_gpio_pinset_a80 = {
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'A', AWIN_A80_PIO_PA_GMAC_FUNC, AWIN_A80_PIO_PA_GMAC_PINS, 0, 3
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};
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CFATTACH_DECL_NEW(awin_gige, sizeof(struct awin_gige_softc),
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awin_gige_match, awin_gige_attach, NULL, NULL);
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static int
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awin_gige_match(device_t parent, cfdata_t cf, void *aux)
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{
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const struct awin_gpio_pinset *pinset =
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awin_chip_id() == AWIN_CHIP_ID_A31 ?
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&awin_gige_gpio_pinset_a31 : &awin_gige_gpio_pinset;
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struct awinio_attach_args * const aio __diagused = aux;
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const struct awin_locators * const loc __diagused = &aio->aio_loc;
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if (cf->cf_flags & 1)
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return 0;
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KASSERT(!strcmp(cf->cf_name, loc->loc_name));
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KASSERT(cf->cf_loc[AWINIOCF_PORT] == AWINIOCF_PORT_DEFAULT
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|| cf->cf_loc[AWINIOCF_PORT] == loc->loc_port);
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if (!awin_gpio_pinset_available(pinset))
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return 0;
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return 1;
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}
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static void
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awin_gige_attach(device_t parent, device_t self, void *aux)
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{
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struct awin_gige_softc * const sc = device_private(self);
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struct awinio_attach_args * const aio = aux;
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const struct awin_locators * const loc = &aio->aio_loc;
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struct awin_gpio_pinset pinset;
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prop_dictionary_t cfg = device_properties(self);
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uint32_t clkreg;
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const char *phy_type, *pin_name;
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bus_space_handle_t bsh;
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switch (awin_chip_id()) {
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case AWIN_CHIP_ID_A80:
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bsh = aio->aio_a80_core2_bsh;
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pinset = awin_gige_gpio_pinset_a80;
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break;
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case AWIN_CHIP_ID_A31:
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bsh = aio->aio_core_bsh;
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pinset = awin_gige_gpio_pinset_a31;
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break;
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default:
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bsh = aio->aio_core_bsh;
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pinset = awin_gige_gpio_pinset;
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break;
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}
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sc->sc_core.sc_dev = self;
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prop_dictionary_get_uint8(cfg, "pinset-func", &pinset.pinset_func);
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awin_gpio_pinset_acquire(&pinset);
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sc->sc_core.sc_bst = aio->aio_core_bst;
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sc->sc_core.sc_dmat = aio->aio_dmat;
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bus_space_subregion(sc->sc_core.sc_bst, bsh,
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loc->loc_offset, loc->loc_size, &sc->sc_core.sc_bsh);
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aprint_naive("\n");
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aprint_normal(": Gigabit Ethernet Controller\n");
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awin_gige_pmu_init(self);
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/*
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* Interrupt handler
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*/
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sc->sc_ih = intr_establish(loc->loc_intr, IPL_NET, IST_LEVEL,
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awin_gige_intr, sc);
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if (sc->sc_ih == NULL) {
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aprint_error_dev(self, "failed to establish interrupt %d\n",
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loc->loc_intr);
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return;
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}
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aprint_normal_dev(self, "interrupting on irq %d\n",
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loc->loc_intr);
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if (prop_dictionary_get_cstring_nocopy(cfg, "phy-power", &pin_name)) {
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if (awin_gpio_pin_reserve(pin_name, &sc->sc_power_pin)) {
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awin_gpio_pindata_write(&sc->sc_power_pin, 1);
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} else {
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aprint_error_dev(self,
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"failed to reserve GPIO \"%s\"\n", pin_name);
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}
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}
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/*
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* Enable GMAC clock
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*/
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if (awin_chip_id() == AWIN_CHIP_ID_A80) {
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awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
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AWIN_A80_CCU_SCLK_BUS_CLK_GATING1_REG,
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AWIN_A80_CCU_SCLK_BUS_CLK_GATING1_GMAC, 0);
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} else if (awin_chip_id() == AWIN_CHIP_ID_A31) {
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awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
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AWIN_AHB_GATING0_REG, AWIN_A31_AHB_GATING0_GMAC, 0);
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} else if (awin_chip_id() == AWIN_CHIP_ID_A20) {
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awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
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AWIN_AHB_GATING1_REG, AWIN_AHB_GATING1_GMAC, 0);
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}
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/*
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* Soft reset
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*/
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if (awin_chip_id() == AWIN_CHIP_ID_A80) {
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awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
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AWIN_A80_CCU_SCLK_BUS_SOFT_RST1_REG,
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AWIN_A80_CCU_SCLK_BUS_SOFT_RST1_GMAC, 0);
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} else if (awin_chip_id() == AWIN_CHIP_ID_A31) {
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awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
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AWIN_A31_AHB_RESET0_REG,
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AWIN_A31_AHB_RESET0_GMAC_RST, 0);
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}
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/*
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* PHY clock setup
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*/
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if (!prop_dictionary_get_cstring_nocopy(cfg, "phy-type", &phy_type))
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phy_type = "rgmii";
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if (strcmp(phy_type, "rgmii") == 0) {
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clkreg = AWIN_GMAC_CLK_PIT | AWIN_GMAC_CLK_TCS_INT_RGMII;
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} else if (strcmp(phy_type, "rgmii-bpi") == 0) {
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clkreg = AWIN_GMAC_CLK_PIT | AWIN_GMAC_CLK_TCS_INT_RGMII;
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/*
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* These magic bits seem to be necessary for RGMII at gigabit
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* speeds on Banana Pi.
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*/
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clkreg |= __BITS(11,10);
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} else if (strcmp(phy_type, "gmii") == 0) {
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clkreg = AWIN_GMAC_CLK_TCS_INT_RGMII;
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} else if (strcmp(phy_type, "mii") == 0) {
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clkreg = AWIN_GMAC_CLK_TCS_MII;
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} else {
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panic("unknown phy type '%s'", phy_type);
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}
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if (awin_chip_id() == AWIN_CHIP_ID_A80) {
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awin_reg_set_clear(aio->aio_core_bst, aio->aio_a80_core2_bsh,
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AWIN_A80_SYS_CTRL_OFFSET + AWIN_A80_SYS_CTRL_EMAC_CLK_REG,
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clkreg, AWIN_GMAC_CLK_PIT|AWIN_GMAC_CLK_TCS);
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} else if (awin_chip_id() == AWIN_CHIP_ID_A31) {
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awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
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AWIN_A31_GMAC_CLK_REG, clkreg,
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AWIN_GMAC_CLK_PIT|AWIN_GMAC_CLK_TCS);
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} else {
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awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
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AWIN_GMAC_CLK_REG, clkreg,
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AWIN_GMAC_CLK_PIT|AWIN_GMAC_CLK_TCS);
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}
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dwc_gmac_attach(&sc->sc_core, GMAC_MII_CLK_150_250M_DIV102);
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}
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static int
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awin_gige_intr(void *arg)
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{
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struct awin_gige_softc *sc = arg;
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return dwc_gmac_intr(&sc->sc_core);
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}
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static void
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awin_gige_pmu_init(device_t dev)
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{
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if (awin_chip_id() == AWIN_CHIP_ID_A80) {
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#if NAXP806PM > 0
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device_t axp806 = device_find_by_driver_unit("axp806pm", 0);
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if (axp806) {
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struct axp806_ctrl *c = axp806_lookup(axp806, "CLDO1");
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if (c) {
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axp806_set_voltage(c, 3000, 3000);
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axp806_enable(c);
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delay(3000);
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}
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}
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#endif
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#if NAXP809PM > 0
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device_t axp809 = device_find_by_driver_unit("axp809pm", 0);
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if (axp809) {
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struct axp809_ctrl *c = axp809_lookup(axp809, "GPIO1");
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if (c) {
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axp809_enable(c);
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delay(3000);
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}
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}
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#endif
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delay(100000);
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}
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}
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