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165 lines
4.3 KiB
ArmAsm
165 lines
4.3 KiB
ArmAsm
/* $NetBSD: cpufunc_asm.S,v 1.16 2013/08/18 06:28:18 matt Exp $ */
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/*
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* Copyright (c) 1997,1998 Mark Brinicombe.
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* Copyright (c) 1997 Causality Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Causality Limited.
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* 4. The name of Causality Limited may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RiscBSD kernel project
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*
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* cpufunc.S
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*
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* Assembly functions for CPU / MMU / TLB specific operations
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*
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* Created : 30/01/97
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*/
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#include <arm/armreg.h>
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#include <machine/asm.h>
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.text
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.align 0
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ENTRY(cpufunc_nullop)
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RET
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END(cpufunc_nullop)
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/*
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* Generic functions to read the internal coprocessor registers
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*
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* Currently these registers are :
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* c0 - CPU ID
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* c5 - Fault status
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* c6 - Fault address
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*
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*/
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ENTRY(cpufunc_id)
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mrc p15, 0, r0, c0, c0, 0
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RET
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END(cpufunc_id)
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ENTRY(cpu_read_cache_config)
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mrc p15, 0, r0, c0, c0, 1
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RET
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END(cpu_read_cache_config)
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ENTRY(cpu_get_control)
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mrc p15, 0, r0, c1, c0, 0
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RET
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END(cpu_get_control)
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ENTRY(cpufunc_faultstatus)
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mrc p15, 0, r0, c5, c0, 0
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RET
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END(cpufunc_faultstatus)
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ENTRY(cpufunc_faultaddress)
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mrc p15, 0, r0, c6, c0, 0
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RET
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END(cpufunc_faultaddress)
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/*
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* Generic functions to write the internal coprocessor registers
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*
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*
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* Currently these registers are
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* c1 - CPU Control
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* c3 - Domain Access Control
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*
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* All other registers are CPU architecture specific
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*/
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#if 0 /* See below. */
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ENTRY(cpufunc_control)
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mcr p15, 0, r0, c1, c0, 0
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RET
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#endif
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ENTRY(cpufunc_domains)
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mcr p15, 0, r0, c3, c0, 0
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RET
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END(cpufunc_domains)
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/*
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* Generic functions to read/modify/write the internal coprocessor registers
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*
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*
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* Currently these registers are
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* c1 - CPU Control
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*
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* All other registers are CPU architecture specific
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*/
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ENTRY(cpufunc_control)
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mrc p15, 0, r3, c1, c0, 0 /* Read the control register */
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bics r2, r3, r0 /* Clear bits */
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eors r2, r2, r1 /* XOR bits */
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teq r2, r3 /* Only write if there is a change */
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#ifdef __thumb__
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it ne
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#endif
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mcrne p15, 0, r2, c1, c0, 0 /* Write new control register */
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movs r0, r3 /* Return old value */
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RET
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END(cpufunc_control)
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/*
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* other potentially useful software functions are:
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* clean D cache entry and flush I cache entry
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* for the moment use cache_purgeID_E
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*/
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/* Random odd functions */
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/*
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* Function to get the offset of a stored program counter from the
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* instruction doing the store. This offset is defined to be the same
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* for all STRs and STMs on a given implementation. Code based on
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* section 2.4.3 of the ARM ARM (2nd Ed.), with modifications to work
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* in 26-bit modes as well. In Thumb mode, the PC can't be directly
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* stored.
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*/
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ENTRY(get_pc_str_offset)
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#ifdef __thumb__
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mov r0, #4
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RET
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#else
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mov r1, pc /* R1 = addr of following STR */
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mov r8, r8
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push {pc} /* [SP] = . + offset */
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pop {r0}
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subs r0, r0, r1
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RET
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#endif
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END(get_pc_str_offset)
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