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475 lines
13 KiB
C
475 lines
13 KiB
C
/* $NetBSD: db_machdep.c,v 1.23 2015/02/25 13:52:42 joerg Exp $ */
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/*
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* Copyright (c) 1996 Mark Brinicombe
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*
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* Mach Operating System
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* Copyright (c) 1991,1990 Carnegie Mellon University
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* All Rights Reserved.
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*
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* Permission to use, copy, modify and distribute this software and its
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* documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
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* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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#ifdef _KERNEL_OPT
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#include "opt_multiprocessor.h"
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#endif
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.23 2015/02/25 13:52:42 joerg Exp $");
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#include <sys/param.h>
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#include <sys/cpu.h>
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#include <sys/proc.h>
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#include <sys/vnode.h>
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#include <sys/systm.h>
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#include <arm/arm32/db_machdep.h>
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#include <arm/cpufunc.h>
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#include <ddb/db_access.h>
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#include <ddb/db_sym.h>
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#include <ddb/db_output.h>
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#include <ddb/db_variables.h>
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#include <ddb/db_command.h>
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#include <ddb/db_run.h>
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#ifndef _KERNEL
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#include <stddef.h>
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#endif
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#ifdef _KERNEL
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static long nil;
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int db_access_und_sp(const struct db_variable *, db_expr_t *, int);
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int db_access_abt_sp(const struct db_variable *, db_expr_t *, int);
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int db_access_irq_sp(const struct db_variable *, db_expr_t *, int);
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#endif
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static int
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ddb_reg_var(const struct db_variable *v, db_expr_t *ep, int op)
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{
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register_t * const rp = (register_t *)DDB_REGS;
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if (op == DB_VAR_SET) {
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rp[(uintptr_t)v->valuep] = *ep;
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} else {
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*ep = rp[(uintptr_t)v->valuep];
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}
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return 0;
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}
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#define XO(f) ((long *)(offsetof(db_regs_t, f) / sizeof(register_t)))
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const struct db_variable db_regs[] = {
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{ "spsr", XO(tf_spsr), ddb_reg_var, NULL },
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{ "r0", XO(tf_r0), ddb_reg_var, NULL },
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{ "r1", XO(tf_r1), ddb_reg_var, NULL },
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{ "r2", XO(tf_r2), ddb_reg_var, NULL },
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{ "r3", XO(tf_r3), ddb_reg_var, NULL },
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{ "r4", XO(tf_r4), ddb_reg_var, NULL },
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{ "r5", XO(tf_r5), ddb_reg_var, NULL },
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{ "r6", XO(tf_r6), ddb_reg_var, NULL },
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{ "r7", XO(tf_r7), ddb_reg_var, NULL },
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{ "r8", XO(tf_r8), ddb_reg_var, NULL },
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{ "r9", XO(tf_r9), ddb_reg_var, NULL },
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{ "r10", XO(tf_r10), ddb_reg_var, NULL },
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{ "r11", XO(tf_r11), ddb_reg_var, NULL },
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{ "r12", XO(tf_r12), ddb_reg_var, NULL },
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{ "usr_sp", XO(tf_usr_sp), ddb_reg_var, NULL },
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{ "usr_lr", XO(tf_usr_lr), ddb_reg_var, NULL },
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{ "svc_sp", XO(tf_svc_sp), ddb_reg_var, NULL },
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{ "svc_lr", XO(tf_svc_lr), ddb_reg_var, NULL },
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{ "pc", XO(tf_pc), ddb_reg_var, NULL },
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#ifdef _KERNEL
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{ "und_sp", &nil, db_access_und_sp, NULL },
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{ "abt_sp", &nil, db_access_abt_sp, NULL },
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{ "irq_sp", &nil, db_access_irq_sp, NULL },
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#endif
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};
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#undef XO
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const struct db_variable * const db_eregs = db_regs + sizeof(db_regs)/sizeof(db_regs[0]);
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const struct db_command db_machine_command_table[] = {
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{ DDB_ADD_CMD("frame", db_show_frame_cmd, 0,
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"Displays the contents of a trapframe",
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"[address]",
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" address:\taddress of trapfame to display")},
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#ifdef _KERNEL
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{ DDB_ADD_CMD("fault", db_show_fault_cmd, 0,
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"Displays the fault registers",
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NULL,NULL) },
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#endif
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#if defined(_KERNEL) && (defined(CPU_CORTEXA5) || defined(CPU_CORTEXA7))
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{ DDB_ADD_CMD("tlb", db_show_tlb_cmd, 0,
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"Displays the TLB",
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NULL,NULL) },
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#endif
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#if defined(_KERNEL) && defined(MULTIPROCESSOR)
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{ DDB_ADD_CMD("cpu", db_switch_cpu_cmd, 0,
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"switch to a different cpu",
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NULL,NULL) },
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#endif
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#ifdef ARM32_DB_COMMANDS
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ARM32_DB_COMMANDS,
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#endif
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{ DDB_ADD_CMD(NULL, NULL, 0,NULL,NULL,NULL) }
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};
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#ifdef _KERNEL
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int
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db_access_und_sp(const struct db_variable *vp, db_expr_t *valp, int rw)
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{
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if (rw == DB_VAR_GET)
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*valp = get_stackptr(PSR_UND32_MODE);
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return(0);
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}
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int
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db_access_abt_sp(const struct db_variable *vp, db_expr_t *valp, int rw)
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{
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if (rw == DB_VAR_GET)
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*valp = get_stackptr(PSR_ABT32_MODE);
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return(0);
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}
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int
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db_access_irq_sp(const struct db_variable *vp, db_expr_t *valp, int rw)
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{
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if (rw == DB_VAR_GET)
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*valp = get_stackptr(PSR_IRQ32_MODE);
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return(0);
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}
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void
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db_show_fault_cmd(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif)
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{
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db_printf("DFAR=%#x DFSR=%#x IFAR=%#x IFSR=%#x\n",
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armreg_dfar_read(), armreg_dfsr_read(),
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armreg_ifar_read(), armreg_ifsr_read());
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db_printf("CONTEXTIDR=%#x TTBCR=%#x TTBR=%#x\n",
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armreg_contextidr_read(), armreg_ttbcr_read(),
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armreg_ttbr_read());
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}
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#if defined(CPU_CORTEXA5) || defined(CPU_CORTEXA7)
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static void
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tlb_print_common_header(const char *str)
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{
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db_printf("-W/I-- ----VA---- ----PA---- --SIZE-- D AP XN ASD %s\n", str);
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}
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static void
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tlb_print_addr(size_t way, size_t va_index, vaddr_t vpn, paddr_t pfn)
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{
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db_printf("[%1zu:%02zx] 0x%05lx000 0x%05lx000", way, va_index, vpn, pfn);
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}
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static void
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tlb_print_size_domain_prot(const char *sizestr, u_int domain, u_int ap,
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bool xn_p)
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{
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db_printf(" %8s %1x %2d %s", sizestr, domain, ap, (xn_p ? "XN" : "--"));
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}
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static void
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tlb_print_asid(bool ng_p, tlb_asid_t asid)
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{
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if (ng_p) {
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db_printf(" %3d", asid);
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} else {
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db_printf(" ---");
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}
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}
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struct db_tlbinfo {
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vaddr_t (*dti_decode_vpn)(size_t, uint32_t, uint32_t);
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void (*dti_print_header)(void);
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void (*dti_print_entry)(size_t, size_t, uint32_t, uint32_t);
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u_int dti_index;
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};
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#if defined(CPU_CORTEXA5)
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static void
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tlb_print_cortex_a5_header(void)
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{
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tlb_print_common_header(" S TEX C B");
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}
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static vaddr_t
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tlb_decode_cortex_a5_vpn(size_t va_index, uint32_t d0, uint32_t d1)
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{
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const uint64_t d = ((uint64_t)d1 << 32) | d0;
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const u_int size = __SHIFTOUT(d, ARM_A5_TLBDATA_SIZE);
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return __SHIFTOUT(d, ARM_A5_TLBDATA_VA) * (ARM_A5_TLBDATAOP_INDEX + 1)
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+ (va_index << (4*size));
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}
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static void
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tlb_print_cortex_a5_entry(size_t way, size_t va_index, uint32_t d0, uint32_t d1)
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{
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static const char size_strings[4][8] = {
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" 4KB ", " 64KB ", " 1MB ", " 16MB ",
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};
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const uint64_t d = ((uint64_t)d1 << 32) | d0;
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const paddr_t pfn = __SHIFTOUT(d, ARM_A5_TLBDATA_PA);
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const vaddr_t vpn = tlb_decode_cortex_a5_vpn(va_index, d0, d1);
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tlb_print_addr(way, va_index, vpn, pfn);
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const u_int size = __SHIFTOUT(d, ARM_A5_TLBDATA_SIZE);
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const u_int domain = __SHIFTOUT(d, ARM_A5_TLBDATA_DOM);
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const u_int ap = __SHIFTOUT(d, ARM_A5_TLBDATA_AP);
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const bool xn_p = (d & ARM_A5_TLBDATA_XN) != 0;
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tlb_print_size_domain_prot(size_strings[size], domain, ap, xn_p);
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const bool ng_p = (d & ARM_A5_TLBDATA_nG) != 0;
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const tlb_asid_t asid = __SHIFTOUT(d, ARM_A5_TLBDATA_ASID);
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tlb_print_asid(ng_p, asid);
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const u_int tex = __SHIFTOUT(d, ARM_A5_TLBDATA_TEX);
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const bool c_p = (d & ARM_A5_TLBDATA_C) != 0;
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const bool b_p = (d & ARM_A5_TLBDATA_B) != 0;
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const bool s_p = (d & ARM_A5_TLBDATA_S) != 0;
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db_printf(" %c %d %c %c\n", (s_p ? 'S' : '-'), tex,
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(c_p ? 'C' : '-'), (b_p ? 'B' : '-'));
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}
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static const struct db_tlbinfo tlb_cortex_a5_info = {
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.dti_decode_vpn = tlb_decode_cortex_a5_vpn,
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.dti_print_header = tlb_print_cortex_a5_header,
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.dti_print_entry = tlb_print_cortex_a5_entry,
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.dti_index = ARM_A5_TLBDATAOP_INDEX,
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};
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#endif /* CPU_CORTEXA5 */
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#if defined(CPU_CORTEXA7)
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static const char tlb_cortex_a7_esizes[8][8] = {
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" 4KB(S)", " 4KB(L)", "64KB(S)", "64KB(L)",
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" 1MB(S)", " 2MB(L)", "16MB(S)", " 1GB(L)",
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};
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static void
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tlb_print_cortex_a7_header(void)
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{
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tlb_print_common_header("IS --OS- SH");
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}
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static inline vaddr_t
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tlb_decode_cortex_a7_vpn(size_t va_index, uint32_t d0, uint32_t d1)
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{
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const u_int size = __SHIFTOUT(d0, ARM_A7_TLBDATA0_SIZE);
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const u_int shift = (size & 1)
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? ((0x12090400 >> (8*size)) & 0x1f)
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: (2 * size);
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return __SHIFTOUT(d0, ARM_A7_TLBDATA0_VA) * (ARM_A7_TLBDATAOP_INDEX + 1)
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+ (va_index << shift);
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}
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static void
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tlb_print_cortex_a7_entry(size_t way, size_t va_index, uint32_t d0, uint32_t d1)
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{
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const uint32_t d2 = armreg_tlbdata2_read();
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const uint64_t d01 = ((uint64_t)d1 << 32) | d0;
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const uint64_t d12 = ((uint64_t)d2 << 32) | d1;
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const paddr_t pfn = __SHIFTOUT(d12, ARM_A7_TLBDATA12_PA);
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const vaddr_t vpn = tlb_decode_cortex_a7_vpn(va_index, d0, d1);
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tlb_print_addr(way, va_index, vpn, pfn);
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const u_int size = __SHIFTOUT(d0, ARM_A7_TLBDATA0_SIZE);
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const u_int domain = __SHIFTOUT(d2, ARM_A7_TLBDATA2_DOM);
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const u_int ap = __SHIFTOUT(d1, ARM_A7_TLBDATA1_AP);
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const bool xn_p = (d2 & ARM_A7_TLBDATA2_XN1) != 0;
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tlb_print_size_domain_prot(tlb_cortex_a7_esizes[size], domain, ap, xn_p);
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const bool ng_p = (d1 & ARM_A7_TLBDATA1_nG) != 0;
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const tlb_asid_t asid = __SHIFTOUT(d01, ARM_A7_TLBDATA01_ASID);
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tlb_print_asid(ng_p, asid);
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const u_int is = __SHIFTOUT(d2, ARM_A7_TLBDATA2_IS);
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if (is == ARM_A7_TLBDATA2_IS_DSO) {
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u_int mt = __SHIFTOUT(d2, ARM_A7_TLBDATA2_SDO_MT);
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switch (mt) {
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case ARM_A7_TLBDATA2_SDO_MT_D:
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db_printf(" DV\n");
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return;
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case ARM_A7_TLBDATA2_SDO_MT_SO:
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db_printf(" SO\n");
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return;
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default:
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db_printf(" %02u\n", mt);
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return;
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}
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}
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const u_int os = __SHIFTOUT(d2, ARM_A7_TLBDATA2_OS);
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const u_int sh = __SHIFTOUT(d2, ARM_A7_TLBDATA2_SH);
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static const char is_types[3][3] = { "NC", "WB", "WT" };
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static const char os_types[4][6] = { "NC", "WB+WA", "WT", "WB" };
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static const char sh_types[4][3] = { "NS", "na", "OS", "IS" };
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db_printf(" %2s %5s %2s\n", is_types[is], os_types[os], sh_types[sh]);
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}
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static const struct db_tlbinfo tlb_cortex_a7_info = {
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.dti_decode_vpn = tlb_decode_cortex_a7_vpn,
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.dti_print_header = tlb_print_cortex_a7_header,
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.dti_print_entry = tlb_print_cortex_a7_entry,
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.dti_index = ARM_A7_TLBDATAOP_INDEX,
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};
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#endif /* CPU_CORTEXA7 */
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static inline const struct db_tlbinfo *
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tlb_lookup_tlbinfo(void)
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{
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#if defined(CPU_CORTEXA5) && defined(CPU_CORTEXA7)
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const bool cortex_a5_p = CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid);
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const bool cortex_a7_p = CPU_ID_CORTEX_A7_P(curcpu()->ci_arm_cpuid);
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#elif defined(CPU_CORTEXA5)
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const bool cortex_a5_p = true;
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#else
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const bool cortex_a7_p = true;
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#endif
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#ifdef CPU_CORTEXA5
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if (cortex_a5_p) {
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return &tlb_cortex_a5_info;
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}
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#endif
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#ifdef CPU_CORTEXA7
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if (cortex_a7_p) {
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return &tlb_cortex_a7_info;
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}
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#endif
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return NULL;
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}
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void
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db_show_tlb_cmd(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif)
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{
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const struct db_tlbinfo * const dti = tlb_lookup_tlbinfo();
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if (have_addr) {
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const vaddr_t vpn = (vaddr_t)addr >> L2_S_SHIFT;
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const u_int va_index = vpn & dti->dti_index;
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for (size_t way = 0; way < 2; way++) {
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armreg_tlbdataop_write(
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__SHIFTIN(va_index, dti->dti_index)
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| __SHIFTIN(way, ARM_TLBDATAOP_WAY));
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arm_isb();
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const uint32_t d0 = armreg_tlbdata0_read();
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const uint32_t d1 = armreg_tlbdata1_read();
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if ((d0 & ARM_TLBDATA_VALID)
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&& vpn == (*dti->dti_decode_vpn)(va_index, d0, d1)) {
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(*dti->dti_print_header)();
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(*dti->dti_print_entry)(way, va_index, d0, d1);
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return;
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}
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}
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db_printf("VA %#"DDB_EXPR_FMT"x not found in TLB\n", addr);
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return;
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}
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bool first = true;
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size_t n = 0;
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for (size_t va_index = 0; va_index <= dti->dti_index; va_index++) {
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for (size_t way = 0; way < 2; way++) {
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armreg_tlbdataop_write(
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__SHIFTIN(way, ARM_TLBDATAOP_WAY)
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| __SHIFTIN(va_index, dti->dti_index));
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arm_isb();
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const uint32_t d0 = armreg_tlbdata0_read();
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const uint32_t d1 = armreg_tlbdata1_read();
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if (d0 & ARM_TLBDATA_VALID) {
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if (first) {
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(*dti->dti_print_header)();
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first = false;
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}
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(*dti->dti_print_entry)(way, va_index, d0, d1);
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n++;
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}
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}
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}
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db_printf("%zu TLB valid entries found\n", n);
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}
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#endif /* CPU_CORTEXA5 || CPU_CORTEXA7 */
|
|
#endif /* _KERNEL */
|
|
|
|
|
|
void
|
|
db_show_frame_cmd(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif)
|
|
{
|
|
struct trapframe *frame;
|
|
|
|
if (!have_addr) {
|
|
db_printf("frame address must be specified\n");
|
|
return;
|
|
}
|
|
|
|
frame = (struct trapframe *)addr;
|
|
|
|
db_printf("frame address = %08x ", (u_int)frame);
|
|
db_printf("spsr=%08x\n", frame->tf_spsr);
|
|
db_printf("r0 =%08x r1 =%08x r2 =%08x r3 =%08x\n",
|
|
frame->tf_r0, frame->tf_r1, frame->tf_r2, frame->tf_r3);
|
|
db_printf("r4 =%08x r5 =%08x r6 =%08x r7 =%08x\n",
|
|
frame->tf_r4, frame->tf_r5, frame->tf_r6, frame->tf_r7);
|
|
db_printf("r8 =%08x r9 =%08x r10=%08x r11=%08x\n",
|
|
frame->tf_r8, frame->tf_r9, frame->tf_r10, frame->tf_r11);
|
|
db_printf("r12=%08x r13=%08x r14=%08x r15=%08x\n",
|
|
frame->tf_r12, frame->tf_usr_sp, frame->tf_usr_lr, frame->tf_pc);
|
|
db_printf("slr=%08x\n", frame->tf_svc_lr);
|
|
}
|
|
|
|
#if defined(_KERNEL) && defined(MULTIPROCESSOR)
|
|
void
|
|
db_switch_cpu_cmd(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif)
|
|
{
|
|
if (addr >= maxcpus) {
|
|
db_printf("cpu %"DDB_EXPR_FMT"d out of range", addr);
|
|
return;
|
|
}
|
|
struct cpu_info *new_ci = cpu_lookup(addr);
|
|
if (new_ci == NULL) {
|
|
db_printf("cpu %"DDB_EXPR_FMT"d does not exist", addr);
|
|
return;
|
|
}
|
|
if (DDB_REGS->tf_spsr & PSR_T_bit) {
|
|
DDB_REGS->tf_pc -= 2; /* XXX */
|
|
} else {
|
|
DDB_REGS->tf_pc -= 4;
|
|
}
|
|
db_newcpu = new_ci;
|
|
db_continue_cmd(0, false, 0, "");
|
|
}
|
|
#endif
|