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188 lines
6.2 KiB
ArmAsm
188 lines
6.2 KiB
ArmAsm
/* $NetBSD: irq_dispatch.S,v 1.16 2015/06/02 14:06:16 matt Exp $ */
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/*
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* Copyright (c) 2002 Fujitsu Component Limited
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* Copyright (c) 2002 Genetec Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of The Fujitsu Component Limited nor the name of
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* Genetec corporation may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
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* CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
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* CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 2002, 2003 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "assym.h"
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#include <machine/asm.h>
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#include <arm/locore.h>
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#include "opt_arm_intr_impl.h"
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#ifdef ARM_INTR_IMPL
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#include ARM_INTR_IMPL
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#else
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#error ARM_INTR_IMPL not defined
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#endif
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#ifndef ARM_IRQ_HANDLER
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#error ARM_IRQ_HANDLER not defined
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#endif
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/*
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* irq_entry:
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* Main entry point for the IRQ vector. This is a generic version
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* which can be used by different platforms.
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*/
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.text
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.p2align 5
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ARM_ASENTRY_NP(irq_entry)
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sub lr, lr, #0x00000004 /* Adjust the lr */
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PUSHFRAMEINSVC /* Push an interrupt frame */
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ENABLE_ALIGNMENT_FAULTS /* finishes with curcpu() in r4 */
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#ifdef _ARM_ARCH_7
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clrex /* force all strex to fail */
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dmb /* synchronize memory writes */
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#endif
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/*
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* Increment the interrupt nesting depth and call the interrupt
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* dispatch routine. We've pushed a frame, so we can safely use
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* callee-saved regs here. We use the following registers, which
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* we expect to persist:
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*
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* r4 address of current cpu_info
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* r6 old value of `ci_intr_depth'
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*/
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ldr r6, [r4, #CI_INTR_DEPTH]
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add r1, r6, #1
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str r1, [r4, #CI_INTR_DEPTH]
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mov r0, sp /* arg for dispatcher */
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bl ARM_IRQ_HANDLER
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/*
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* Restore the old interrupt depth value (which should be the
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* same as decrementing it at this point).
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*/
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str r6, [r4, #CI_INTR_DEPTH]
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LOCK_CAS_CHECK
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DO_AST_AND_RESTORE_ALIGNMENT_FAULTS
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PULLFRAMEFROMSVCANDEXIT
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#ifdef __thumb__
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subs pc, lr, #0 /* Exit */
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#else
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movs pc, lr /* Exit */
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#endif
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.align 0
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LOCK_CAS_CHECK_LOCALS
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AST_ALIGNMENT_FAULT_LOCALS
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ASEND(irq_entry)
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.p2align 5
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ARM_ASENTRY_NP(irq_idle_entry)
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PUSHIDLEFRAME
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/*
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* Increment the interrupt nesting depth and call the interrupt
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* dispatch routine. We've pushed a frame, so we can safely use
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* callee-saved regs here. We use the following registers, which
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* we expect to persist:
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*
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* r4 address of current cpu_info
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* r6 old value of `ci_intr_depth'
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*/
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GET_CURCPU(r4)
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ldr r6, [r4, #CI_INTR_DEPTH]
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add r1, r6, #1
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str r1, [r4, #CI_INTR_DEPTH]
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#ifdef _ARM_ARCH_7
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clrex /* force all strex to fail */
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dmb /* synchronize memory writes */
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#endif
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mov r0, sp /* arg for dispatcher */
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bl ARM_IRQ_HANDLER
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/*
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* Restore the old interrupt depth value (which should be the
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* same as decrementing it at this point).
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*/
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str r6, [r4, #CI_INTR_DEPTH]
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#if defined(__HAVE_FAST_SOFTINTS) && !defined(__HAVE_PIC_FAST_SOFTINTS)
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ldr r2, [r4, #CI_CPL] /* Get current priority level */
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ldr r3, [r4, #CI_SOFTINTS] /* Get pending softint mask */
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#endif
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PULLIDLEFRAME /* restore r4, r6, sp, lr */
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#if defined(__HAVE_FAST_SOFTINTS) && !defined(__HAVE_PIC_FAST_SOFTINTS)
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lsrs r3, r3, r2 /* shift mask by cpl */
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bne _C_LABEL(dosoftints) /* dosoftints(void) */
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#endif
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RET
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ASEND(irq_idle_entry)
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