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94 lines
3.9 KiB
C
94 lines
3.9 KiB
C
/* $NetBSD: a9tmr_reg.h,v 1.1 2012/09/01 00:03:14 matt Exp $ */
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/*-
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* ARM MPCORE Global Timer Register Definitions
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*
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* These registers are accessible through a dedicated internal bus.
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* All accesses must be done in a little-endian manner.
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* The base address of the pages containing these registers is defined
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* by the pins PERIPHBASE[31:13] which can be obtained by doing a
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* MRC p15,4,<Rd>,c15,c0,0; Read Configuration Base Address Register
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* (except cortex-A9 uniprocessor)
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*
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*/
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#ifndef _ARM_CORTEX_A9TMR_REG_H_
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#define _ARM_CORTEX_A9TMR_REG_H_
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#define TMR_GLOBAL_BASE 0x0200 // Offset in PeriphBase
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#define TMR_PRIVATE_BASE 0x0600
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#define TMR_WDOG_BASE 0x0620
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#define TMR_GLOBAL_SIZE 0x0100
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#define TMR_PRIVATE_SIZE 0x0020
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#define TMR_WDOG_SIZE 0x0020
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/*
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* F(timer) = PeriphClk / ((PreScaler_Value + 1) * Load_Value + 1))
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*/
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#define TMR_LOAD 0x0000 // Timer Load Register
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#define TMR_CTR 0x0004 // Timer Counter Register
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#define TMR_CTL 0x0008 // Timer Control Register
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#define TMR_INT 0x000C // Timer Interrupt Status
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#define TMR_RST 0x0010 // Timer Reset Status (WDOG only)
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#define TMR_WDOGDIS 0x0014 // [WO] Timer Disable (WDOG only)
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#define TMR_CTL_PRESCALER __BITS(15,8)
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#define TMR_CTL_WDOG_MODE __BIT(3) // WDOG mode
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#define TMR_CTL_INT_ENABLE __BIT(2) // INT 29/30 is enabled
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#define TMR_CTL_AUTO_RELOAD __BIT(1)
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#define TMR_CTL_ENABLE __BIT(0)
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#define TMR_INT_EVENT __BIT(0) // [W1C] timer reached 0
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#define TMR_RST_EVENT __BIT(0) // [W1C] wdog timer reached 0
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#define TMR_WDOG_DISABLE_MAGIC1 0x12345678
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#define TMR_WDOG_DISABLE_MAGIC2 0x87654321
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/*
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* Global Timer is a 64-bit incrementing counter. As much as we'd like to
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* be able to use LDRD for loading the 64-bit counter, we aren't allowed to.
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*/
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#define TMR_GBL_CTR_L 0x000 // Global Timer 64-bit Lower Value
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#define TMR_GBL_CTR_U 0x004 // Global Timer 64-bit Upper Timer
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#define TMR_GBL_CTL 0x008 // Global Timer Control
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#define TMR_GBL_INT 0x00c // [L] Global Timer Interrupt Status
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#define TMR_GBL_CMP_L 0x010 // [L] Global Timer 64-bit Comparator Low
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#define TMR_GBL_CMP_H 0x014 // [L] Global Timer 64-bit Comparator High
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#define TMR_GBL_AUTOINC 0x018 // [L] Global Timer Auto-Increment
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#define TMR_GBL_CTL_PRESCALER __BIT(15,8)
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#define TMR_GBL_CTL_AUTO_INC __BIT(3) // Auto Increment is enabled
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#define TMR_GBL_CTL_INT_ENABLE __BIT(2) // [banked] INT 27 is enabled
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#define TMR_GBL_CTL_CMP_ENABLE __BIT(1) // [banked]
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#define TMR_GBL_CTL_ENABLE __BIT(0)
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#endif /* !_ARM_CORTEX_A9TMR_REG_H_ */
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