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156 lines
5.3 KiB
C
156 lines
5.3 KiB
C
/* $NetBSD: pl310_reg.h,v 1.4 2014/03/22 17:12:20 reinoud Exp $ */
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/*-
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_CORTEX_PL310_REG_H_
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#define _ARM_CORTEX_PL310_REG_H_
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/*
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* ARM PL310 L2 Cache Controller
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* Used by Cortex cores
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*/
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#define L2C_CACHE_ID 0x000
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#define CACHE_ID_IMPL __BITS(31,24)
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#define CACHE_ID_ID __BITS(15,10)
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#define CACHE_ID_PART __BITS(9,6)
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#define CACHE_ID_PART_PL310 3
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#define CACHE_ID_REV __BITS(5,0)
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#define CACHE_ID_REV_R3P3 9
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#define CACHE_ID_REV_R3P2 8
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#define L2C_CACHE_TYPE 0x004
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#define CACHE_TYPE_DATA_BANKING __BIT(31)
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#define CACHE_TYPE_CTYPE __BITS(28,25)
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#define CACHE_TYPE_HARVARD __BIT(24)
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#define CACHE_TYPE_DSIZE __BITS(23,12)
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#define CACHE_TYPE_ISIZE __BITS(11,0)
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#define CACHE_TYPE_xWAYSIZE __BITS(10,8)
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#define CACHE_TYPE_xASSOC __BIT(6)
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#define CACHE_TYPE_xLINESIZE __BITS(5,0)
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#define L2C_CTL 0x100
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#define CTL_ENABLE __BIT(1)
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#define L2C_AUXCTL 0x104
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#define AUXCTL_RSVD31 __BIT(31)
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#define AUXCTL_EARLY_BRESP_EN __BIT(30)
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#define AUXCTL_I_PREFETCH __BIT(29)
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#define AUXCTL_D_PREFETCH __BIT(28)
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#define AUXCTL_NS_INT_ACC_CTL __BIT(27)
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#define AUXCTL_NS_INT_LOCK_EN __BIT(26)
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#define AUXCTL_CACHE_REPL_RR __BIT(25)
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#define AUXCTL_FORCE_WA __BITS(24,23)
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#define AUXCTL_FORCE_WA_AWCACHE 0
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#define AUXCTL_FORCE_WA_NEVER 1
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#define AUXCTL_FORCE_WA_ALWAYS 2
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#define AUXCTL_FORCE_WA_0 3
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#define AUXCTL_SHARED_ATT_OVR __BIT(22)
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#define AUXCTL_PARITY_EN __BIT(21)
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#define AUXCTL_EVT_MON_BUS_EN __BIT(20)
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#define AUXCTL_WAY_SIZE __BITS(19,17)
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#define AUXCTL_WAY_SIZE_RSVD0 0
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#define AUXCTL_WAY_SIZE_16KB 1
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#define AUXCTL_WAY_SIZE_32KB 2
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#define AUXCTL_WAY_SIZE_64KB 3
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#define AUXCTL_WAY_SIZE_128KB 4
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#define AUXCTL_WAY_SIZE_256KB 5
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#define AUXCTL_WAY_SIZE_512KB 6
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#define AUXCTL_WAY_SIZE_RSVD7 7
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#define AUXCTL_ASSOCIATIVITY __BIT(16)
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#define AUXCTL_SH_ATTR_INV_ENA __BIT(13)
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#define AUXCTL_EXCL_CACHE_CFG __BIT(12)
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#define AUXCTL_ST_BUF_DEV_LIM_EN __BIT(11)
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#define AUXCTL_HIPRO_SO_DEV_EN __BIT(10)
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#define AUXCTL_FULL_LINE_WR0 __BIT(0)
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#define L2C_TAGRAM_CTL 0x108
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#define L2C_DATARAM_CTL 0x10c
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#define L2C_EV_CTR_CTL 0x200
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#define L2C_EV_CTR1_CTL 0x204
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#define L2C_EV_CTR0_CTL 0x208
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#define L2C_EV_CTR1 0x20c
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#define L2C_EV_CTR0 0x210
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#define L2C_INT_MASK 0x214
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#define L2C_INT_MASK_STS 0x218
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#define L2C_INT_RAW_STS 0x21c
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#define L2C_INT_CLR 0x220
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#define L2C_CACHE_SYNC 0x730
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#define L2C_INV_PA 0x770
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#define L2C_INV_WAY 0x77c
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#define L2C_CLEAN_PA 0x7b0
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#define L2C_CLEAN_INDEX 0x7b8
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#define L2C_CLEAN_WAY 0x7bc
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#define L2C_CLEAN_INV_PA 0x7f0
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#define L2C_CLEAN_INV_INDEX 0x7f8
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#define L2C_CLEAN_INV_WAY 0x7fc
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#define L2C_D_LOCKDOWN0 0x900
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#define L2C_I_LOCKDOWN0 0x904
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#define L2C_D_LOCKDOWN1 0x908
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#define L2C_I_LOCKDOWN1 0x90c
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#define L2C_D_LOCKDOWN2 0x910
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#define L2C_I_LOCKDOWN2 0x914
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#define L2C_D_LOCKDOWN3 0x918
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#define L2C_I_LOCKDOWN3 0x91c
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#define L2C_D_LOCKDOWN4 0x920
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#define L2C_I_LOCKDOWN4 0x924
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#define L2C_D_LOCKDOWN5 0x928
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#define L2C_I_LOCKDOWN5 0x92c
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#define L2C_D_LOCKDOWN6 0x930
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#define L2C_I_LOCKDOWN6 0x934
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#define L2C_D_LOCKDOWN7 0x938
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#define L2C_I_LOCKDOWN7 0x93c
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#define L2C_LOCK_LINE_EN 0x950
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#define L2C_UNLOCK_WAY 0x954
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#define L2C_ADDR_FILTER_START 0xc00
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#define L2C_ADDR_FILTER_END 0xc04
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#define L2C_DEBUG_CTL 0xf40
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#define L2C_PREFETCH_CTL 0xf60
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#define PREFETCHCTL_DBLLINEF_EN __BIT(30)
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#define PREFETCHCTL_INSTRPREF_EN __BIT(29)
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#define PREFETCHCTL_DATAPREF_EN __BIT(28)
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#define PREFETCHCTL_DBLLINEF_WRAP_DA __BIT(27)
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#define PREFETCHCTL_PREF_DROP_EN __BIT(24)
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#define PREFETCHCTL_INCRDBL_LINEF_EN __BIT(23)
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#define PREFETCHCTL_NOSAMEID_EXCL_SEQ_EN __BIT(21)
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#define PREFETCHCTL_PREFETCH_OFFSET_0 0
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#define PREFETCHCTL_PREFETCH_OFFSET_7 7
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#define PREFETCHCTL_PREFETCH_OFFSET_15 15
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#define PREFETCHCTL_PREFETCH_OFFSET_23 23
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#define PREFETCHCTL_PREFETCH_OFFSET_31 31
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#define L2C_POWER_CTL 0xf80
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#define POWERCTL_DYNCLKGATE __BIT(1)
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#define POWERCTL_STANDBY __BIT(0)
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#endif /* _ARM_CORTEX_PL310_REG_H_ */
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