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72 lines
3.0 KiB
C
72 lines
3.0 KiB
C
/* $NetBSD: scu_reg.h,v 1.1 2012/09/01 00:03:14 matt Exp $ */
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/*-
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_CORTEX_SCUREG_H_
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#define _ARM_CORTEX_SCUREG_H_
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/*
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* ARM Snoop Control Unit Definitions
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* Used by Cortex-A5 and Cortex-A9
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*/
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#define SCU_CTL 0x00 // SCU Control Register
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#define SCU_CFG 0x04 // SCU Configuration Register
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#define SCU_CPU_PWR_STS 0x08 // SCU CPU Power Status
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#define SCU_INV_ALL_REG 0x0c // SCU Invalidate All Registers in Secure State
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#define SCU_FILTER_START 0x40 // Filtering Start Address
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#define SCU_FILTER_END 0x44 // Filtering End Address
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#define SCU_ACCESS_CONTROL 0x50 // SCU Access Control
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#define SCU_NS_ACCESS_CONTROL 0x54 // SCU Non-Secure Access Control
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#define SCU_CTL_IC_STANDBY_ENA __BIT(6)
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#define SCU_CTL_SCU_STANDBY_ENA __BIT(5)
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#define SCU_CTL_FORCE_PORT0_ENA __BIT(4)
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#define SCU_CTL_SPECULATIVE_LINEFILL_ENA __BIT(3)
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#define SCU_CTL_SCU_RAM_PARITY_ENA __BIT(2)
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#define SCU_CTL_ADDR_FILTER_ENA __BIT(1)
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#define SCU_CTL_SCU_ENA __BIT(0)
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#define SCU_CFG_TAG_RAM_SIZE_CPUn(n) __BITS(9+2*(n),8+2*(n))
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#define SCU_CFG_TAG_RAM_SIZE_CPU3 __BITS(15,14)
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#define SCU_CFG_TAG_RAM_SIZE_CPU2 __BITS(13,12)
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#define SCU_CFG_TAG_RAM_SIZE_CPU1 __BITS(11,10)
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#define SCU_CFG_TAG_RAM_SIZE_CPU0 __BITS(9,8)
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#define SCU_CFG_TAG_RAM_SIZE_16KB 0
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#define SCU_CFG_TAG_RAM_SIZE_32KB 1
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#define SCU_CFG_TAG_RAM_SIZE_64KB 2
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#define SCU_CFG_CPUn_SMP(n) __BIT(4+(n))
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#define SCU_CFG_CPU3_SMP __BIT(7)
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#define SCU_CFG_CPU2_SMP __BIT(6)
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#define SCU_CFG_CPU1_SMP __BIT(5)
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#define SCU_CFG_CPU0_SMP __BIT(4)
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#define SCU_CFG_CPUMAX __BITS(0,1) // # of CPU - 1
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#endif /* _ARM_CORTEX_SCUREG_H_ */
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