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318 lines
9.9 KiB
C
318 lines
9.9 KiB
C
/* $Id: imx23_clkctrlreg.h,v 1.2 2013/10/07 17:36:40 matt Exp $ */
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/*
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Petri Laakso.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_IMX_IMX23_CLKCTRLREG_H_
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#define _ARM_IMX_IMX23_CLKCTRLREG_H_
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#include <sys/cdefs.h>
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#define HW_CLKCTRL_BASE 0x80040000
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#define HW_CLKCTRL_SIZE 0x2000
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/*
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* PLL Control Register 0.
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*/
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#define HW_CLKCTRL_PLLCTRL0 0x000
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#define HW_CLKCTRL_PLLCTRL0_SET 0x004
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#define HW_CLKCTRL_PLLCTRL0_CLR 0x008
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#define HW_CLKCTRL_PLLCTRL0_TOG 0x00C
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#define HW_CLKCTRL_PLLCTRL0_RSRVD6 __BITS(31, 30)
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#define HW_CLKCTRL_PLLCTRL0_LFR_SEL __BITS(29, 28)
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#define HW_CLKCTRL_PLLCTRL0_RSRVD5 __BITS(27, 26)
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#define HW_CLKCTRL_PLLCTRL0_CP_SEL __BITS(25, 24)
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#define HW_CLKCTRL_PLLCTRL0_RSRVD4 __BITS(23, 22)
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#define HW_CLKCTRL_PLLCTRL0_DIV_SEL __BITS(21, 20)
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#define HW_CLKCTRL_PLLCTRL0_RSRVD3 __BIT(19)
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#define HW_CLKCTRL_PLLCTRL0_EN_USB_CLKS __BIT(18)
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#define HW_CLKCTRL_PLLCTRL0_RSRVD2 __BIT(17)
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#define HW_CLKCTRL_PLLCTRL0_POWER __BIT(16)
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#define HW_CLKCTRL_PLLCTRL0_RSRVD1 __BITS(15, 0)
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/*
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* PLL Control Register 1.
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*/
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#define HW_CLKCTRL_PLLCTRL1 0x010
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#define HW_CLKCTRL_PLLCTRL1_LOCK __BIT(31)
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#define HW_CLKCTRL_PLLCTRL1_FORCE_LOCK __BIT(30)
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#define HW_CLKCTRL_PLLCTRL1_RSRVD1 __BITS(29, 16)
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#define HW_CLKCTRL_PLLCTRL1_LOCK_COUNT __BITS(15, 0)
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/*
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* CPU Clock Control Register.
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*/
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#define HW_CLKCTRL_CPU 0x020
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#define HW_CLKCTRL_CPU_SET 0x024
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#define HW_CLKCTRL_CPU_CLR 0x028
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#define HW_CLKCTRL_CPU_TOG 0x02c
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#define HW_CLKCTRL_CPU_RSVD6 __BITS(31, 30)
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#define HW_CLKCTRL_CPU_BUSY_REF_XTAL __BIT(29)
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#define HW_CLKCTRL_CPU_BUSY_REF_CPU __BIT(28)
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#define HW_CLKCTRL_CPU_RSVD5 __BIT(27)
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#define HW_CLKCTRL_CPU_DIV_XTAL_FRAC_EN __BIT(26)
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#define HW_CLKCTRL_CPU_DIV_XTAL __BITS(25, 16)
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#define HW_CLKCTRL_CPU_RSVD4 __BITS(15, 13)
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#define HW_CLKCTRL_CPU_INTERRUPT_WAIT __BIT(12)
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#define HW_CLKCTRL_CPU_RSVD3 __BIT(11)
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#define HW_CLKCTRL_CPU_RSVD2 __BIT(10)
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#define HW_CLKCTRL_CPU_RSVD1 __BITS(9, 6)
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#define HW_CLKCTRL_CPU_DIV_CPU __BITS(5, 0)
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/*
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* AHB, APBH Bus Clock Control Register.
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*/
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#define HW_CLKCTRL_HBUS 0x030
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#define HW_CLKCTRL_HBUS_SET 0x034
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#define HW_CLKCTRL_HBUS_CLR 0x038
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#define HW_CLKCTRL_HBUS_TOG 0x03c
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#define HW_CLKCTRL_HBUS_RSRVD4 __BITS(31, 30)
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#define HW_CLKCTRL_HBUS_BUSY __BIT(29)
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#define HW_CLKCTRL_HBUS_DCP_AS_ENABLE __BIT(28)
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#define HW_CLKCTRL_HBUS_PXP_AS_ENABLE __BIT(27)
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#define HW_CLKCTRL_HBUS_APBHDMA_AS_ENABLE __BIT(26)
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#define HW_CLKCTRL_HBUS_APBXDMA_AS_ENABLE __BIT(25)
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#define HW_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE __BIT(24)
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#define HW_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE __BIT(23)
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#define HW_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE __BIT(22)
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#define HW_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE __BIT(21)
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#define HW_CLKCTRL_HBUS_AUTO_SLOW_MODE __BIT(20)
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#define HW_CLKCTRL_HBUS_RSRVD2 __BIT(19)
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#define HW_CLKCTRL_HBUS_SLOW_DIV __BITS(18, 16)
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#define HW_CLKCTRL_HBUS_RSRVD1 __BITS(15, 6)
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#define HW_CLKCTRL_HBUS_DIV_FRAC_EN __BIT(5)
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#define HW_CLKCTRL_HBUS_DIV __BITS(4, 0)
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/*
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* APBX Clock Control Register.
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*/
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#define HW_CLKCTRL_XBUS 0x040
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#define HW_CLKCTRL_XBUS_BUSY __BIT(31)
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#define HW_CLKCTRL_XBUS_RSVD2 __BITS(30, 11)
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#define HW_CLKCTRL_XBUS_RSVD1 __BIT(10)
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#define HW_CLKCTRL_XBUS_DIV __BITS(9, 0)
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/*
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* XTAL Clock Control Register.
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*/
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#define HW_CLKCTRL_XTAL 0x050
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#define HW_CLKCTRL_XTAL_SET 0x054
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#define HW_CLKCTRL_XTAL_CLR 0x058
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#define HW_CLKCTRL_XTAL_TOG 0x05C
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#define HW_CLKCTRL_XTAL_UART_CLK_GATE __BIT(31)
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#define HW_CLKCTRL_XTAL_FILT_CLK24M_GATE __BIT(30)
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#define HW_CLKCTRL_XTAL_PWM_CLK24M_GATE __BIT(29)
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#define HW_CLKCTRL_XTAL_DRI_CLK24M_GATE __BIT(28)
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#define HW_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE __BIT(27)
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#define HW_CLKCTRL_XTAL_TIMROT_CLK32K_GATE __BIT(26)
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#define HW_CLKCTRL_XTAL_RSRVD1 __BITS(25, 2)
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#define HW_CLKCTRL_XTAL_DIV_UART __BITS(1, 0)
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/*
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* PIX (LCDIF) Clock Control Register.
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*/
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#define HW_CLKCTRL_PIX 0x060
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#define HW_CLKCTRL_PIX_CLKGATE __BIT(31)
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#define HW_CLKCTRL_PIX_RSRVD2 __BIT(30)
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#define HW_CLKCTRL_PIX_BUSY __BIT(29)
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#define HW_CLKCTRL_PIX_RSRVD1 __BITS(28, 13)
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#define HW_CLKCTRL_PIX_DIV_FRAC_EN __BIT(12)
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#define HW_CLKCTRL_PIX_DIV __BITS(11, 0)
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/*
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* Synchronous Serial Port Clock Control Register.
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*/
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#define HW_CLKCTRL_SSP 0x070
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#define HW_CLKCTRL_SSP_CLKGATE __BIT(31)
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#define HW_CLKCTRL_SSP_RSVD3 __BIT(30)
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#define HW_CLKCTRL_SSP_BUSY __BIT(29)
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#define HW_CLKCTRL_SSP_RSVD2 __BITS(28, 10)
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#define HW_CLKCTRL_SSP_RSVD1 __BIT(9)
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#define HW_CLKCTRL_SSP_DIV __BITS(8, 0)
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/*
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* General-Purpose Media Interface Clock Control Register.
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*/
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#define HW_CLKCTRL_GPMI 0x080
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#define HW_CLKCTRL_GPMI_CLKGATE __BIT(31)
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#define HW_CLKCTRL_GPMI_RSVD3 __BIT(30)
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#define HW_CLKCTRL_GPMI_BUSY __BIT(29)
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#define HW_CLKCTRL_GPMI_RSVD2 __BITS(28, 11)
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#define HW_CLKCTRL_GPMI_RSVD1 __BIT(10)
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#define HW_CLKCTRL_GPMI_DIV __BIT(9, 0)
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/*
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* SPDIF Clock Control Register.
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*/
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#define HW_CLKCTRL_SPDIF 0x090
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#define HW_CLKCTRL_SPDIF_CLKGATE __BIT(31)
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#define HW_CLKCTRL_SPDIF_RSRVD __BITS(30, 0)
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/*
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* EMI Clock Control Register.
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*/
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#define HW_CLKCTRL_EMI 0x0a0
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#define HW_CLKCTRL_EMI_CLKGATE __BIT(31)
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#define HW_CLKCTRL_EMI_SYNC_MODE_EN __BIT(30)
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#define HW_CLKCTRL_EMI_BUSY_REF_XTAL __BIT(29)
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#define HW_CLKCTRL_EMI_BUSY_REF_EMI __BIT(28)
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#define HW_CLKCTRL_EMI_BUSY_REF_CPU __BIT(27)
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#define HW_CLKCTRL_EMI_BUSY_SYNC_MODE __BIT(26)
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#define HW_CLKCTRL_EMI_RSVD5 __BITS(25, 18)
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#define HW_CLKCTRL_EMI_RSVD4 __BIT(17)
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#define HW_CLKCTRL_EMI_RSVD3 __BIT(16)
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#define HW_CLKCTRL_EMI_RSVD2 __BITS(15, 12)
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#define HW_CLKCTRL_EMI_DIV_XTAL __BITS(11, 8)
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#define HW_CLKCTRL_EMI_RSVD1 __BITS(7, 6)
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#define HW_CLKCTRL_EMI_DIV_EMI __BITS(5, 0)
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/*
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* SAIF Clock Control Register.
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*/
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#define HW_CLKCTRL_SAIF 0x0c0
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#define HW_CLKCTRL_SAIF_CLKGATE __BIT(31)
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#define HW_CLKCTRL_SAIF_RSRVD2 __BIT(30)
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#define HW_CLKCTRL_SAIF_BUSY __BIT(29)
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#define HW_CLKCTRL_SAIF_RSRVD1 __BITS(28, 17)
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#define HW_CLKCTRL_SAIF_DIV_FRAC_EN __BIT(16)
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#define HW_CLKCTRL_SAIF_DIV __BITS(15, 0)
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/*
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* TV Encoder Clock Control Register.
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*/
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#define HW_CLKCTRL_TV 0x0d0
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#define HW_CLKCTRL_TV_CLK_TV108M_GATE __BIT(31)
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#define HW_CLKCTRL_TV_CLK_TV_GATE __BIT(30)
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#define HW_CLKCTRL_TV_RSRVD __BITS(29, 0)
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/*
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* ETM Clock Control Register.
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*/
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#define HW_CLKCTRL_ETM 0x0e0
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#define HW_CLKCTRL_ETM_CLKGATE __BIT(31)
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#define HW_CLKCTRL_ETM_RSRVD2 __BIT(30)
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#define HW_CLKCTRL_ETM_BUSY __BIT(29)
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#define HW_CLKCTRL_ETM_RSRVD1 __BITS(28, 7)
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#define HW_CLKCTRL_ETM_DIV_FRAC_EN __BIT(6)
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#define HW_CLKCTRL_ETM_DIV __BITs(5, 0)
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/*
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* Fractional Clock Control Register.
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*/
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#define HW_CLKCTRL_FRAC 0x0f0
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#define HW_CLKCTRL_FRAC_SET 0x0f4
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#define HW_CLKCTRL_FRAC_CLR 0x0f8
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#define HW_CLKCTRL_FRAC_TOG 0x0fC
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#define HW_CLKCTRL_FRAC_CLKGATEIO __BIT(31)
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#define HW_CLKCTRL_FRAC_IO_STABLE __BIT(30)
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#define HW_CLKCTRL_FRAC_IOFRAC __BITS(29, 24)
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#define HW_CLKCTRL_FRAC_CLKGATEPIX __BIT(23)
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#define HW_CLKCTRL_FRAC_PIX_STABLE __BIT(22)
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#define HW_CLKCTRL_FRAC_PIXFRAC __BITS(21, 16)
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#define HW_CLKCTRL_FRAC_CLKGATEEMI __BIT(15)
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#define HW_CLKCTRL_FRAC_EMI_STABLE __BIT(14)
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#define HW_CLKCTRL_FRAC_EMIFRAC __BITS(13, 8)
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#define HW_CLKCTRL_FRAC_CLKGATECPU __BIT(7)
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#define HW_CLKCTRL_FRAC_CPU_STABLE __BIT(6)
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#define HW_CLKCTRL_FRAC_CPUFRAC __BITS(5, 0)
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/*
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* Fractional Clock Control Register 1.
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*/
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#define HW_CLKCTRL_FRAC1 0x100
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#define HW_CLKCTRL_FRAC1_SET 0x104
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#define HW_CLKCTRL_FRAC1_CLR 0x108
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#define HW_CLKCTRL_FRAC1_TOG 0x10C
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#define HW_CLKCTRL_FRAC1_CLKGATEVID __BIT(31)
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#define HW_CLKCTRL_FRAC1_VID_STABLE __BIT(30)
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#define HW_CLKCTRL_FRAC1_RSRVD1 __BITS(29, 0)
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/*
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* Clock Frequency Sequence Control Register.
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*/
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#define HW_CLKCTRL_CLKSEQ 0x110
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#define HW_CLKCTRL_CLKSEQ_SET 0x114
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#define HW_CLKCTRL_CLKSEQ_CLR 0x118
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#define HW_CLKCTRL_CLKSEQ_TOG 0x11c
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#define HW_CLKCTRL_CLKSEQ_RSRVD1 __BITS(31, 9)
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#define HW_CLKCTRL_CLKSEQ_BYPASS_ETM __BIT(8)
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#define HW_CLKCTRL_CLKSEQ_BYPASS_CPU __BIT(7)
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#define HW_CLKCTRL_CLKSEQ_BYPASS_EMI __BIT(6)
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#define HW_CLKCTRL_CLKSEQ_BYPASS_SSP __BIT(5)
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#define HW_CLKCTRL_CLKSEQ_BYPASS_GPMI __BIT(4)
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#define HW_CLKCTRL_CLKSEQ_BYPASS_IR __BIT(3)
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#define HW_CLKCTRL_CLKSEQ_RSRVD0 __BIT(2)
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#define HW_CLKCTRL_CLKSEQ_BYPASS_PIX __BIT(1)
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#define HW_CLKCTRL_CLKSEQ_BYPASS_SAIF __BIT(0)
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/*
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* System Software Reset Register.
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*/
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#define HW_CLKCTRL_RESET 0x120
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#define HW_CLKCTRL_RESET_RSRVD __BITS(31, 2)
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#define HW_CLKCTRL_RESET_CHIP __BIT(1)
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#define HW_CLKCTRL_RESET_DIG __BIT(0)
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/*
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* CLKCTRL Status.
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*/
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#define HW_CLKCTRL_STATUS 0x130
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#define HW_CLKCTRL_STATUS_CPU_LIMIT __BITS(31, 30)
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#define HW_CLKCTRL_STATUS_RSRVD __BITS(29, 0)
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/*
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* CLKCTRL Version Register.
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*/
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#define HW_CLKCTRL_VERSION 0x140
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#define HW_CLKCTRL_VERSION_MAJOR __BITS(31, 24)
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#define HW_CLKCTRL_VERSION_MINOR __BITS(23, 16)
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#define HW_CLKCTRL_VERSION_STEP __BITS(15, 0)
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#endif /* !_ARM_IMX_IMX23_CLKCTRLREG_H_ */
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