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609 lines
13 KiB
C
609 lines
13 KiB
C
/* $Id: imx23_pinctrl.c,v 1.1 2013/10/07 17:36:40 matt Exp $ */
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/*
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* Copyright (c) 2013 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Petri Laakso.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/types.h>
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#include <sys/bus.h>
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#include <sys/cdefs.h>
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#include <sys/device.h>
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#include <sys/errno.h>
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#include <sys/gpio.h>
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#include <dev/gpio/gpiovar.h>
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#include <arm/imx/imx23_pinctrlreg.h>
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#include <arm/imx/imx23_pinctrlvar.h>
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#include <arm/imx/imx23var.h>
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#define GPIO_PINS 96
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typedef struct pinctrl_softc {
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device_t sc_dev;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_hdl;
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struct gpio_chipset_tag gc;
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gpio_pin_t pins[GPIO_PINS];
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} *pinctrl_softc_t;
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static int pinctrl_match(device_t, cfdata_t, void *);
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static void pinctrl_attach(device_t, device_t, void *);
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static int pinctrl_activate(device_t, enum devact);
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#if notyet
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static void pinctrl_reset(struct pinctrl_softc *);
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#endif
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static void pinctrl_init(struct pinctrl_softc *);
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static int pinctrl_gp_gc_open(void *, device_t);
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static void pinctrl_gp_gc_close(void *, device_t);
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static int pinctrl_gp_pin_read(void *, int);
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static void pinctrl_gp_pin_write(void *, int, int);
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static void pinctrl_gp_pin_ctl(void *, int, int);
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static pinctrl_softc_t _sc = NULL;
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CFATTACH_DECL3_NEW(pinctrl,
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sizeof(struct pinctrl_softc),
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pinctrl_match,
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pinctrl_attach,
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NULL,
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pinctrl_activate,
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NULL,
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NULL,
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0
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);
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#define GPIO_PIN_CAP (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_INOUT | \
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GPIO_PIN_PULLUP | GPIO_PIN_SET)
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/*
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* Supported capabilities for each GPIO pin.
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*/
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const static int pin_caps[GPIO_PINS] = {
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/*
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* HW_PINCTRL_MUXSEL0
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*/
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/* PIN 0 */
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GPIO_PIN_CAP,
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/* PIN 1 */
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GPIO_PIN_CAP,
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/* PIN 2 */
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GPIO_PIN_CAP,
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/* PIN 3 */
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GPIO_PIN_CAP,
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/* PIN 4 */
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GPIO_PIN_CAP,
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/* PIN 5 */
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GPIO_PIN_CAP,
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/* PIN 6 */
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GPIO_PIN_CAP,
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/* PIN 7 */
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GPIO_PIN_CAP,
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/* PIN 8 */
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GPIO_PIN_CAP,
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/* PIN 9 */
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GPIO_PIN_CAP,
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/* PIN 10 */
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GPIO_PIN_CAP,
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/* PIN 11 */
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GPIO_PIN_CAP,
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/* PIN 12 */
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GPIO_PIN_CAP,
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/* PIN 13 */
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GPIO_PIN_CAP,
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/* PIN 14 */
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GPIO_PIN_CAP,
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/* PIN 15 */
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GPIO_PIN_CAP,
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/*
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* HW_PINCTRL_MUXSEL1
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*/
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/* PIN 16 */
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GPIO_PIN_CAP,
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/* PIN 17 */
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0, /* Reserved for powering OLinuXino MAXI/MINI USB hub. */
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/* PIN 18 */
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GPIO_PIN_CAP,
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/* PIN 19 */
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GPIO_PIN_CAP,
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/* PIN 20 */
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GPIO_PIN_CAP,
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/* PIN 21 */
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GPIO_PIN_CAP,
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/* PIN 22 */
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GPIO_PIN_CAP,
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/* PIN 23 */
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GPIO_PIN_CAP,
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/* PIN 24 */
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GPIO_PIN_CAP,
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/* PIN 25 */
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GPIO_PIN_CAP,
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/* PIN 26 */
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GPIO_PIN_CAP,
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/* PIN 27 */
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GPIO_PIN_CAP,
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/* PIN 28 */
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GPIO_PIN_CAP,
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/* PIN 29 */
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GPIO_PIN_CAP,
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/* PIN 30 */
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GPIO_PIN_CAP,
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/* PIN 31 */
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GPIO_PIN_CAP,
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/*
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* HW_PINCTRL_MUXSEL2
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*/
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/* PIN 32 */
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GPIO_PIN_CAP,
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/* PIN 33 */
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GPIO_PIN_CAP,
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/* PIN 34 */
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GPIO_PIN_CAP,
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/* PIN 35 */
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GPIO_PIN_CAP,
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/* PIN 36 */
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GPIO_PIN_CAP,
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/* PIN 37 */
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GPIO_PIN_CAP,
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/* PIN 38 */
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GPIO_PIN_CAP,
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/* PIN 39 */
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GPIO_PIN_CAP,
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/* PIN 40 */
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GPIO_PIN_CAP,
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/* PIN 41 */
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GPIO_PIN_CAP,
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/* PIN 42 */
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GPIO_PIN_CAP,
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/* PIN 43 */
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GPIO_PIN_CAP,
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/* PIN 44 */
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GPIO_PIN_CAP,
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/* PIN 45 */
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GPIO_PIN_CAP,
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/* PIN 46 */
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GPIO_PIN_CAP,
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/* PIN 47 */
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GPIO_PIN_CAP,
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/*
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* HW_PINCTRL_MUXSEL3
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*/
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/* PIN 48 */
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GPIO_PIN_CAP,
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/* PIN 49 */
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GPIO_PIN_CAP,
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/* PIN 50 */
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GPIO_PIN_CAP,
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/* PIN 51 */
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GPIO_PIN_CAP,
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/* PIN 52 */
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GPIO_PIN_CAP,
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/* PIN 53 */
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GPIO_PIN_CAP,
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/* PIN 54 */
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GPIO_PIN_CAP,
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/* PIN 55 */
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GPIO_PIN_CAP,
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/* PIN 56 */
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GPIO_PIN_CAP,
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/* PIN 57 */
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GPIO_PIN_CAP,
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/* PIN 58 */
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GPIO_PIN_CAP,
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/* PIN 59 */
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GPIO_PIN_CAP,
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/* PIN 60 */
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GPIO_PIN_CAP,
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/* PIN 61 */
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GPIO_PIN_CAP,
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/* PIN 62 */
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GPIO_PIN_CAP,
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/* PIN 63 */
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0, /* Reserved. */
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/*
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* HW_PINCTRL_MUXSEL4
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*/
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/* PIN 64 */
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GPIO_PIN_CAP,
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/* PIN 65 */
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GPIO_PIN_CAP,
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/* PIN 66 */
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GPIO_PIN_CAP,
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/* PIN 67 */
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GPIO_PIN_CAP,
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/* PIN 68 */
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GPIO_PIN_CAP,
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/* PIN 69 */
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GPIO_PIN_CAP,
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/* PIN 70 */
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GPIO_PIN_CAP,
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/* PIN 71 */
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GPIO_PIN_CAP,
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/* PIN 72 */
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GPIO_PIN_CAP,
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/* PIN 73 */
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0, /* From this on reserved for EMI (DRAM) pins. */
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/* PIN 74 */
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0,
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/* PIN 75 */
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0,
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/* PIN 76 */
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0,
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/* PIN 77 */
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0,
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/* PIN 78 */
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0,
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/* PIN 79 */
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0,
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/*
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* HW_PINCTRL_MUXSEL5
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*/
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/* PIN 80 */
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0,
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/* PIN 81 */
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0,
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/* PIN 82 */
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0,
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/* PIN 83 */
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0,
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/* PIN 84 */
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0,
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/* PIN 85 */
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0,
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/* PIN 86 */
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0,
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/* PIN 87 */
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0,
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/* PIN 88 */
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0,
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/* PIN 89 */
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0,
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/* PIN 90 */
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0,
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/* PIN 91 */
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0,
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/* PIN 92 */
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0,
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/* PIN 93 */
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0,
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/* PIN 94 */
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0,
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/* PIN 95 */
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0
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};
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#define PINCTRL_RD(sc, reg) \
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bus_space_read_4(sc->sc_iot, sc->sc_hdl, (reg))
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#define PINCTRL_WR(sc, reg, val) \
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bus_space_write_4(sc->sc_iot, sc->sc_hdl, (reg), (val))
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/*
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* Macros to map pin numbers to registers and bit fields.
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*/
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#define MUXSEL_REG_SIZE 0x10
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#define PIN2MUXSEL_REG(pin) \
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((pin / 16) * MUXSEL_REG_SIZE + HW_PINCTRL_MUXSEL0)
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#define PIN2MUXSEL_SET_REG(pin) \
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((pin / 16) * MUXSEL_REG_SIZE + HW_PINCTRL_MUXSEL0_SET)
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#define PIN2MUXSEL_CLR_REG(pin) \
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((pin / 16) * MUXSEL_REG_SIZE + HW_PINCTRL_MUXSEL0_CLR)
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#define PIN2MUXSEL_MASK(pin) (3<<(pin % 16 * 2))
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#define DRIVE_REG_SIZE 0x10
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#define PIN2DRIVE_REG(pin) \
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((pin / 8) * DRIVE_REG_SIZE + HW_PINCTRL_DRIVE0)
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#define PIN2DRIVE_SET_REG(pin) \
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((pin / 8) * DRIVE_REG_SIZE + HW_PINCTRL_DRIVE0_SET)
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#define PIN2DRIVE_CLR_REG(pin) \
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((pin / 8) * DRIVE_REG_SIZE + HW_PINCTRL_DRIVE0_CLR)
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#define PIN2DRIVE_MASK(pin) (3<<(pin % 8 * 4))
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#define PULL_REG_SIZE 0x10
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#define PIN2PULL_REG(pin) \
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((pin / 32) * PULL_REG_SIZE + HW_PINCTRL_PULL0)
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#define PIN2PULL_SET_REG(pin) \
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((pin / 32) * PULL_REG_SIZE + HW_PINCTRL_PULL0_SET)
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#define PIN2PULL_CLR_REG(pin) \
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((pin / 32) * PULL_REG_SIZE + HW_PINCTRL_PULL0_CLR)
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#define PIN2PULL_MASK(pin) (1<<(pin % 32))
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#define DOUT_REG_SIZE 0x10
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#define PIN2DOUT_REG(pin) \
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((pin / 32) * DOUT_REG_SIZE + HW_PINCTRL_DOUT0)
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#define PIN2DOUT_SET_REG(pin) \
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((pin / 32) * DOUT_REG_SIZE + HW_PINCTRL_DOUT0_SET)
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#define PIN2DOUT_CLR_REG(pin) \
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((pin / 32) * DOUT_REG_SIZE + HW_PINCTRL_DOUT0_CLR)
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#define PIN2DOUT_MASK(pin) (1<<(pin % 32))
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#define DIN_REG_SIZE 0x10
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#define PIN2DIN_REG(pin) ((pin / 32) * DIN_REG_SIZE + HW_PINCTRL_DIN0)
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#define PIN2DIN_MASK(pin) (1<<(pin % 32))
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#define DOE_REG_SIZE 0x10
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#define PIN2DOE_REG(pin) \
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((pin / 32) * DOE_REG_SIZE + HW_PINCTRL_DOE0)
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#define PIN2DOE_SET_REG(pin) \
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((pin / 32) * DOE_REG_SIZE + HW_PINCTRL_DOE0_SET)
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#define PIN2DOE_CLR_REG(pin) \
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((pin / 32) * DOE_REG_SIZE + HW_PINCTRL_DOE0_CLR)
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#define PIN2DOE_MASK(pin) (1<<(pin % 32))
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#define DRIVE_STRENGTH_4MA 0
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#define DRIVE_STRENGTH_8MA 1
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#define DRIVE_STRENGTH_12MA 2
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#define MUXEL_GPIO_MODE 3
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#define PINCTRL_SOFT_RST_LOOP 455 /* At least 1 us ... */
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static int
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pinctrl_match(device_t parent, cfdata_t match, void *aux)
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{
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struct apb_attach_args *aa = aux;
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if ((aa->aa_addr == HW_PINCTRL_BASE) &&
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(aa->aa_size == HW_PINCTRL_SIZE))
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return 1;
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return 0;
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}
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static void
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pinctrl_attach(device_t parent, device_t self, void *aux)
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{
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struct pinctrl_softc *sc = device_private(self);
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struct apb_attach_args *aa = aux;
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static int pinctrl_attached = 0;
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sc->sc_dev = self;
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sc->sc_iot = aa->aa_iot;
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if (pinctrl_attached) {
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aprint_error_dev(sc->sc_dev, "already attached\n");
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return;
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}
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if (bus_space_map(sc->sc_iot, aa->aa_addr, aa->aa_size, 0,
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&sc->sc_hdl))
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{
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aprint_error_dev(sc->sc_dev, "Unable to map bus space\n");
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return;
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}
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#if notyet
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pinctrl_reset(sc);
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#endif
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pinctrl_init(sc);
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aprint_normal(": PIN MUX & GPIO\n");
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/* Set pin capabilities. */
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int i;
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for(i = 0; i < GPIO_PINS; i++) {
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sc->pins[i].pin_caps = pin_caps[i];
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}
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pinctrl_attached = 1;
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sc->gc.gp_cookie = sc;
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sc->gc.gp_gc_open = pinctrl_gp_gc_open;
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sc->gc.gp_gc_close = pinctrl_gp_gc_close;
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sc->gc.gp_pin_read = pinctrl_gp_pin_read;
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sc->gc.gp_pin_write = pinctrl_gp_pin_write;
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sc->gc.gp_pin_ctl = pinctrl_gp_pin_ctl;
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struct gpiobus_attach_args gpiobus_aa;
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gpiobus_aa.gba_gc = &sc->gc;
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gpiobus_aa.gba_npins = GPIO_PINS;
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gpiobus_aa.gba_pins = sc->pins;
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config_found_ia(self, "gpiobus", &gpiobus_aa, gpiobus_print);
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return;
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}
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static int
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pinctrl_activate(device_t self, enum devact act)
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{
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return EOPNOTSUPP;
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}
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static void
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pinctrl_init(struct pinctrl_softc *sc)
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{
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_sc = sc;
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return;
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}
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#if notyet
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/*
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* Inspired by i.MX23 RM "39.3.10 Correct Way to Soft Reset a Block"
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*/
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static void
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pinctrl_reset(struct pinctrl_softc *sc)
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{
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unsigned int loop;
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/* Prepare for soft-reset by making sure that SFTRST is not currently
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* asserted. Also clear CLKGATE so we can wait for its assertion below.
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*/
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PINCTRL_WR(sc, HW_PINCTRL_CTRL_CLR, HW_PINCTRL_CTRL_SFTRST);
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/* Wait at least a microsecond for SFTRST to deassert. */
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loop = 0;
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while ((PINCTRL_RD(sc, HW_PINCTRL_CTRL) & HW_PINCTRL_CTRL_SFTRST) ||
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(loop < PINCTRL_SOFT_RST_LOOP))
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loop++;
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/* Clear CLKGATE so we can wait for its assertion below. */
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PINCTRL_WR(sc, HW_PINCTRL_CTRL_CLR, HW_PINCTRL_CTRL_CLKGATE);
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/* Soft-reset the block. */
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PINCTRL_WR(sc, HW_PINCTRL_CTRL_SET, HW_PINCTRL_CTRL_SFTRST);
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/* Wait until clock is in the gated state. */
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while (!(PINCTRL_RD(sc, HW_PINCTRL_CTRL) & HW_PINCTRL_CTRL_CLKGATE));
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/* Bring block out of reset. */
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PINCTRL_WR(sc, HW_PINCTRL_CTRL_CLR, HW_PINCTRL_CTRL_SFTRST);
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loop = 0;
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while ((PINCTRL_RD(sc, HW_PINCTRL_CTRL) & HW_PINCTRL_CTRL_SFTRST) ||
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(loop < PINCTRL_SOFT_RST_LOOP))
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loop++;
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PINCTRL_WR(sc, HW_PINCTRL_CTRL_CLR, HW_PINCTRL_CTRL_CLKGATE);
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/* Wait until clock is in the NON-gated state. */
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while (PINCTRL_RD(sc, HW_PINCTRL_CTRL) & HW_PINCTRL_CTRL_CLKGATE);
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return;
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}
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#endif
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/*
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* Enable external USB transceiver/HUB.
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*
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* PIN18/LCD_D17/USB_EN controls reset line of external USB chip on MINI and
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* MAXI boards. We configure this pin to logic 1.
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*/
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void
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pinctrl_en_usb(void)
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{
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struct pinctrl_softc *sc = _sc;
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if (sc == NULL) {
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aprint_error("pinctrl is not initalized");
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return;
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}
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pinctrl_gp_pin_ctl(sc, 17, GPIO_PIN_OUTPUT);
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delay(1000);
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pinctrl_gp_pin_write(sc, 17, 1);
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return;
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}
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static int
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pinctrl_gp_gc_open(void *cookie, device_t dev)
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{
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return 0;
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}
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static void
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pinctrl_gp_gc_close(void *cookie, device_t dev)
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{
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return;
|
|
}
|
|
|
|
static int
|
|
pinctrl_gp_pin_read(void *cookie, int pin)
|
|
{
|
|
int value;
|
|
pinctrl_softc_t sc = (pinctrl_softc_t) cookie;
|
|
|
|
if (PINCTRL_RD(sc, PIN2DIN_REG(pin)) & PIN2DIN_MASK(pin))
|
|
value = 1;
|
|
else
|
|
value = 0;
|
|
|
|
return value;
|
|
}
|
|
|
|
static void
|
|
pinctrl_gp_pin_write(void *cookie, int pin, int value)
|
|
{
|
|
pinctrl_softc_t sc = (pinctrl_softc_t) cookie;
|
|
|
|
if (value)
|
|
PINCTRL_WR(sc, PIN2DOUT_SET_REG(pin), PIN2DOUT_MASK(pin));
|
|
else
|
|
PINCTRL_WR(sc, PIN2DOUT_CLR_REG(pin), PIN2DOUT_MASK(pin));
|
|
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Configure pin as requested in flags.
|
|
*/
|
|
static void
|
|
pinctrl_gp_pin_ctl(void *cookie, int pin, int flags)
|
|
{
|
|
pinctrl_softc_t sc = (pinctrl_softc_t) cookie;
|
|
uint32_t tmpr;
|
|
|
|
/* Enable GPIO pin. */
|
|
tmpr = PINCTRL_RD(sc, PIN2MUXSEL_REG(pin));
|
|
tmpr &= ~PIN2MUXSEL_MASK(pin);
|
|
tmpr |= __SHIFTIN(MUXEL_GPIO_MODE, PIN2MUXSEL_MASK(pin));
|
|
PINCTRL_WR(sc, PIN2MUXSEL_REG(pin), tmpr);
|
|
|
|
/* Configure pin drive strength. */
|
|
tmpr = PINCTRL_RD(sc, PIN2DRIVE_REG(pin));
|
|
tmpr &= ~PIN2DRIVE_MASK(pin);
|
|
tmpr |= __SHIFTIN(DRIVE_STRENGTH_4MA, PIN2DRIVE_MASK(pin));
|
|
PINCTRL_WR(sc, PIN2DRIVE_REG(pin), tmpr);
|
|
|
|
if ((flags & (GPIO_PIN_OUTPUT | GPIO_PIN_INOUT))) {
|
|
/* Configure pullup resistor or gate keeper. */
|
|
if (flags & GPIO_PIN_PULLUP)
|
|
PINCTRL_WR(sc, PIN2PULL_SET_REG(pin),
|
|
PIN2PULL_MASK(pin));
|
|
else
|
|
PINCTRL_WR(sc, PIN2PULL_CLR_REG(pin),
|
|
PIN2PULL_MASK(pin));
|
|
|
|
/* Set initial pin value to logic zero. */
|
|
PINCTRL_WR(sc, PIN2DOUT_CLR_REG(pin), PIN2DOUT_MASK(pin));
|
|
|
|
/* Enable pin output. */
|
|
PINCTRL_WR(sc, PIN2DOE_SET_REG(pin), PIN2DOE_MASK(pin));
|
|
}
|
|
|
|
if (flags & GPIO_PIN_INPUT) {
|
|
/* Disable pin output. */
|
|
PINCTRL_WR(sc, PIN2DOE_CLR_REG(pin), PIN2DOE_MASK(pin));
|
|
|
|
/* Configure pullup resistor or gate keeper. */
|
|
if (flags & GPIO_PIN_PULLUP)
|
|
PINCTRL_WR(sc, PIN2PULL_SET_REG(pin),
|
|
PIN2PULL_MASK(pin));
|
|
else
|
|
PINCTRL_WR(sc, PIN2PULL_CLR_REG(pin),
|
|
PIN2PULL_MASK(pin));
|
|
}
|
|
|
|
return;
|
|
}
|