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334 lines
8.2 KiB
C
334 lines
8.2 KiB
C
/* $Id: imx23_timrot.c,v 1.3 2013/10/07 17:36:40 matt Exp $ */
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/*
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Petri Laakso.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <sys/errno.h>
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#include <sys/systm.h>
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#include <arm/pic/picvar.h>
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#include <arm/imx/imx23_icollreg.h>
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#include <arm/imx/imx23_timrotreg.h>
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#include <arm/imx/imx23var.h>
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extern int hz;
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extern int stathz;
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static int timrot_match(device_t, cfdata_t, void *);
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static void timrot_attach(device_t, device_t, void *);
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static int timrot_activate(device_t, enum devact);
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static void timrot_reset(void);
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/*
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* Timer IRQ handler definitions.
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*/
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static int systimer_irq(void *);
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static int stattimer_irq(void *);
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void cpu_initclocks(void);
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void setstatclockrate(int);
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/* Allocated for each timer instance. */
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struct timrot_softc {
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device_t sc_dev;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_hdl;
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int8_t sc_irq;
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int (*irq_handler)(void *);
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int freq;
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};
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static bus_space_tag_t timrot_iot;
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static bus_space_handle_t timrot_hdl;
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CFATTACH_DECL3_NEW(timrot,
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sizeof(struct timrot_softc),
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timrot_match,
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timrot_attach,
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NULL,
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timrot_activate,
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NULL,
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NULL,
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0);
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#define MAX_TIMERS 4
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#define SYS_TIMER 0
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#define STAT_TIMER 1
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#define SCHED_TIMER 2
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struct timrot_softc *timer_sc[MAX_TIMERS];
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static void timer_init(struct timrot_softc *);
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#define TIMROT_SOFT_RST_LOOP 455 /* At least 1 us ... */
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#define TIMROT_READ(reg) \
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bus_space_read_4(timrot_iot, timrot_hdl, (reg))
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#define TIMROT_WRITE(reg, val) \
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bus_space_write_4(timrot_iot, timrot_hdl, (reg), (val))
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#define TIMER_REGS_SIZE 0x20
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#define TIMER_CTRL 0x00
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#define TIMER_CTRL_SET 0x04
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#define TIMER_CTRL_CLR 0x08
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#define TIMER_CTRL_TOG 0x0C
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#define TIMER_COUNT 0x10
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#define TIMER_READ(sc, reg) \
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bus_space_read_4(sc->sc_iot, sc->sc_hdl, (reg))
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#define TIMER_WRITE(sc, reg, val) \
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bus_space_write_4(sc->sc_iot, sc->sc_hdl, (reg), (val))
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#define TIMER_WRITE_2(sc, reg, val) \
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bus_space_write_2(sc->sc_iot, sc->sc_hdl, (reg), (val))
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#define SELECT_32KHZ 0x8 /* Use 32kHz clock source. */
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#define SOURCE_32KHZ_HZ 32000 /* Above source in Hz. */
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#define IRQ HW_TIMROT_TIMCTRL0_IRQ
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#define IRQ_EN HW_TIMROT_TIMCTRL0_IRQ_EN
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#define UPDATE HW_TIMROT_TIMCTRL0_UPDATE
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#define RELOAD HW_TIMROT_TIMCTRL0_RELOAD
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static int
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timrot_match(device_t parent, cfdata_t match, void *aux)
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{
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struct apb_attach_args *aa = aux;
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if ((aa->aa_addr == HW_TIMROT_BASE + HW_TIMROT_TIMCTRL0
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&& aa->aa_size == TIMER_REGS_SIZE))
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return 1;
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if ((aa->aa_addr == HW_TIMROT_BASE + HW_TIMROT_TIMCTRL1
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&& aa->aa_size == TIMER_REGS_SIZE))
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return 1;
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#if 0
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if ((aa->aa_addr == HW_TIMROT_BASE + HW_TIMROT_TIMCTRL2
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&& aa->aa_size == TIMER_REGS_SIZE))
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return 1;
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if ((aa->aa_addr == HW_TIMROT_BASE + HW_TIMROT_TIMCTRL3
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&& aa->aa_size == TIMER_REGS_SIZE))
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return 1;
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#endif
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return 0;
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}
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static void
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timrot_attach(device_t parent, device_t self, void *aux)
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{
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struct apb_attach_args *aa = aux;
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struct timrot_softc *sc = device_private(self);
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static int timrot_attached = 0;
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if (!timrot_attached) {
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timrot_iot = aa->aa_iot;
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if (bus_space_map(timrot_iot, HW_TIMROT_BASE, HW_TIMROT_SIZE,
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0, &timrot_hdl)) {
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aprint_error_dev(sc->sc_dev,
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"unable to map bus space\n");
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return;
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}
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timrot_reset();
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timrot_attached = 1;
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}
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if (aa->aa_addr == HW_TIMROT_BASE + HW_TIMROT_TIMCTRL0
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&& aa->aa_size == TIMER_REGS_SIZE
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&& timer_sc[SYS_TIMER] == NULL) {
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if (bus_space_subregion(timrot_iot, timrot_hdl,
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HW_TIMROT_TIMCTRL0, TIMER_REGS_SIZE,
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&sc->sc_hdl)) {
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aprint_error_dev(sc->sc_dev,
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"unable to map subregion\n");
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return;
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}
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sc->sc_iot = aa->aa_iot;
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sc->sc_irq = aa->aa_irq;
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sc->irq_handler = &systimer_irq;
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sc->freq = hz;
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timer_sc[SYS_TIMER] = sc;
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aprint_normal("\n");
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} else if (aa->aa_addr == HW_TIMROT_BASE + HW_TIMROT_TIMCTRL1
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&& aa->aa_size == TIMER_REGS_SIZE
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&& timer_sc[STAT_TIMER] == NULL) {
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if (bus_space_subregion(timrot_iot, timrot_hdl,
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HW_TIMROT_TIMCTRL1, TIMER_REGS_SIZE, &sc->sc_hdl)) {
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aprint_error_dev(sc->sc_dev,
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"unable to map subregion\n");
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return;
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}
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sc->sc_iot = aa->aa_iot;
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sc->sc_irq = aa->aa_irq;
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sc->irq_handler = &stattimer_irq;
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stathz = (hz>>1);
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sc->freq = stathz;
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timer_sc[STAT_TIMER] = sc;
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aprint_normal("\n");
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}
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return;
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}
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static int
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timrot_activate(device_t self, enum devact act)
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{
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return EOPNOTSUPP;
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}
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/*
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* cpu_initclock is called once at the boot time.
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*/
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void
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cpu_initclocks(void)
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{
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if (timer_sc[SYS_TIMER] != NULL)
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timer_init(timer_sc[SYS_TIMER]);
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if (timer_sc[STAT_TIMER] != NULL)
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timer_init(timer_sc[STAT_TIMER]);
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return;
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}
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/*
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* Change statclock rate when profiling takes place.
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*/
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void
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setstatclockrate(int newhz)
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{
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struct timrot_softc *sc = timer_sc[STAT_TIMER];
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sc->freq = newhz;
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TIMER_WRITE_2(sc, TIMER_COUNT,
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__SHIFTIN(SOURCE_32KHZ_HZ / sc->freq - 1,
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HW_TIMROT_TIMCOUNT0_FIXED_COUNT));
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return;
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}
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/*
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* Generic timer initialization function.
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*/
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static void
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timer_init(struct timrot_softc *sc)
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{
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uint32_t ctrl;
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TIMER_WRITE_2(sc, TIMER_COUNT,
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__SHIFTIN(SOURCE_32KHZ_HZ / sc->freq - 1,
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HW_TIMROT_TIMCOUNT0_FIXED_COUNT));
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ctrl = IRQ_EN | UPDATE | RELOAD | SELECT_32KHZ;
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TIMER_WRITE(sc, TIMER_CTRL, ctrl);
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intr_establish(sc->sc_irq, IPL_SCHED, IST_LEVEL, sc->irq_handler, NULL);
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return;
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}
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/*
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* Timer IRQ handlers.
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*/
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static int
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systimer_irq(void *frame)
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{
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hardclock(frame);
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TIMER_WRITE(timer_sc[SYS_TIMER], TIMER_CTRL_CLR, IRQ);
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return 1;
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}
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static int
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stattimer_irq(void *frame)
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{
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statclock(frame);
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TIMER_WRITE(timer_sc[STAT_TIMER], TIMER_CTRL_CLR, IRQ);
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return 1;
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}
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/*
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* Reset the TIMROT block.
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*
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* Inspired by i.MX23 RM "39.3.10 Correct Way to Soft Reset a Block"
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*/
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static void
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timrot_reset(void)
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{
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unsigned int loop;
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/* Prepare for soft-reset by making sure that SFTRST is not currently
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* asserted. Also clear CLKGATE so we can wait for its assertion below.
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*/
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TIMROT_WRITE(HW_TIMROT_ROTCTRL_CLR, HW_TIMROT_ROTCTRL_SFTRST);
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/* Wait at least a microsecond for SFTRST to deassert. */
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loop = 0;
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while ((TIMROT_READ(HW_TIMROT_ROTCTRL) & HW_TIMROT_ROTCTRL_SFTRST) ||
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(loop < TIMROT_SOFT_RST_LOOP))
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loop++;
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/* Clear CLKGATE so we can wait for its assertion below. */
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TIMROT_WRITE(HW_TIMROT_ROTCTRL_CLR, HW_TIMROT_ROTCTRL_CLKGATE);
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/* Soft-reset the block. */
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TIMROT_WRITE(HW_TIMROT_ROTCTRL_SET, HW_TIMROT_ROTCTRL_SFTRST);
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/* Wait until clock is in the gated state. */
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while (!(TIMROT_READ(HW_TIMROT_ROTCTRL) & HW_TIMROT_ROTCTRL_CLKGATE));
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/* Bring block out of reset. */
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TIMROT_WRITE(HW_TIMROT_ROTCTRL_CLR, HW_TIMROT_ROTCTRL_SFTRST);
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loop = 0;
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while ((TIMROT_READ(HW_TIMROT_ROTCTRL) & HW_TIMROT_ROTCTRL_SFTRST) ||
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(loop < TIMROT_SOFT_RST_LOOP))
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loop++;
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TIMROT_WRITE(HW_TIMROT_ROTCTRL_CLR, HW_TIMROT_ROTCTRL_CLKGATE);
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/* Wait until clock is in the NON-gated state. */
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while (TIMROT_READ(HW_TIMROT_ROTCTRL) & HW_TIMROT_ROTCTRL_CLKGATE);
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return;
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}
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