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https://github.com/Stichting-MINIX-Research-Foundation/netbsd.git
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244 lines
7.4 KiB
C
244 lines
7.4 KiB
C
/* $Id: imx23_uartdbgreg.h,v 1.1 2012/11/20 19:06:14 jkunz Exp $ */
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/*
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Petri Laakso.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_IMX_IMX23_UARTDBGREG_H_
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#define _ARM_IMX_IMX23_UARTDBGREG_H_
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#ifdef _LOCORE
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#include <machine/asm.h>
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#else
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#include <sys/cdefs.h>
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#endif /* !_LOCORE */
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#define HW_UARTDBG_BASE 0x80070000
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#define HW_UARTDBG_SIZE 0x00002000 /* 8kB */
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/*
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* UART Data Register.
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*/
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#define HW_UARTDBGDR 0x000
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#define HW_UARTDBGDR_UNAVAILABLE __BITS(31, 16)
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#define HW_UARTDBGDR_RESERVED __BITS(15, 12)
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#define HW_UARTDBGDR_OE __BIT(11)
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#define HW_UARTDBGDR_BE __BIT(10)
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#define HW_UARTDBGDR_PE __BIT(9)
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#define HW_UARTDBGDR_FE __BIT(8)
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#define HW_UARTDBGDR_DATA __BITS(7,0)
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/*
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* UART Receive Status Register.
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*/
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#define HW_UARTDBGRSR_ECR 0x004
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#define HW_UARTDBGRSR_ECR_UNAVAILABLE __BITS(31, 8)
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#define HW_UARTDBGRSR_ECR_EC __BITS(7, 4)
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#define HW_UARTDBGRSR_ECR_OE __BIT(3)
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#define HW_UARTDBGRSR_ECR_BE __BIT(2)
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#define HW_UARTDBGRSR_ECR_PE __BIT(1)
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#define HW_UARTDBGRSR_ECR_FE __BIT(0)
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/*
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* UART Flag Register.
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*/
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#define HW_UARTDBGFR 0x018
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#define HW_UARTDBGFR_RUNAVAILABLE __BITS(31, 16)
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#define HW_UARTDBGFR_RESERVED __BITS(15, 9)
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#define HW_UARTDBGFR_RI __BIT(8)
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#define HW_UARTDBGFR_TXFE __BIT(7)
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#define HW_UARTDBGFR_RXFF __BIT(6)
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#define HW_UARTDBGFR_TXFF __BIT(5)
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#define HW_UARTDBGFR_RXFE __BIT(4)
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#define HW_UARTDBGFR_BUSY __BIT(3)
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#define HW_UARTDBGFR_DCD __BIT(2)
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#define HW_UARTDBGFR_DSR __BIT(1)
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#define HW_UARTDBGFR_CTS __BIT(0)
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/*
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* UART IrDA Low-Power Counter Register.
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*/
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#define HW_UARTDBGILPR 0x020
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#define HW_UARTDBGILPR_UNAVAILABLE __BITS(31, 8)
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#define HW_UARTDBGILPR_ILPDVSR __BIT(7, 0)
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/*
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* UART Integer Baud Rate Divisor Register.
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*/
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#define HW_UARTDBGIBRD 0x024
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#define HW_UARTDBGIBRD_UNAVAILABLE __BITS(31, 16)
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#define HW_UARTDBGIBRD_BAUD_DIVINT __BITS(15, 0)
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/*
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* UART Fractional Baud Rate Divisor Register.
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*/
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#define HW_UARTDBGFBRD 0x028
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#define HW_UARTDBGFBRD_UNAVAILABLE __BITS(31, 8)
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#define HW_UARTDBGFBRD_RESERVED __BITS(7, 6)
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#define HW_UARTDBGFBRD_BAUD_DIVFRAC __BITS(5, 0)
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/*
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* UART Line Control Register.
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*/
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#define HW_UARTDBGLCR_H 0x02C
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#define HW_UARTDBGLCR_H_UNAVAILABLE __BITS(31, 16)
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#define HW_UARTDBGLCR_H_RESERVED __BITS(15, 8)
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#define HW_UARTDBGLCR_H_SPS __BIT(7)
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#define HW_UARTDBGLCR_H_WLEN __BITS(6, 5)
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#define HW_UARTDBGLCR_H_FEN __BIT(4)
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#define HW_UARTDBGLCR_H_STP2 __BIT(3)
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#define HW_UARTDBGLCR_H_EPS __BIT(2)
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#define HW_UARTDBGLCR_H_PEN __BIT(1)
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#define HW_UARTDBGLCR_H_BRK __BIT(0)
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/*
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* UART Control Register.
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*/
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#define HW_UARTDBGCR 0x030
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#define HW_UARTDBGCR_UNAVAILABLE __BITS(31, 16)
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#define HW_UARTDBGCR_CTSEN __BIT(15)
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#define HW_UARTDBGCR_RTSEN __BIT(14)
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#define HW_UARTDBGCR_OUT2 __BIT(13)
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#define HW_UARTDBGCR_OUT1 __BIT(12)
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#define HW_UARTDBGCR_RTS __BIT(11)
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#define HW_UARTDBGCR_DTR __BIT(10)
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#define HW_UARTDBGCR_RXE __BIT(9)
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#define HW_UARTDBGCR_TXE __BIT(8)
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#define HW_UARTDBGCR_LBE __BIT(7)
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#define HW_UARTDBGCR_RESERVED __BITS(6, 3)
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#define HW_UARTDBGCR_SIRLP __BIT(2)
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#define HW_UARTDBGCR_SIREN __BIT(1)
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#define HW_UARTDBGCR_UARTEN __BIT(0)
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/*
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* UART Interrupt FIFO Level Select Register.
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*/
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#define HW_UARTDBGIFLS 0x034
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#define HW_UARTDBGIFLS_UNAVAILABLE __BITS(31, 16)
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#define HW_UARTDBGIFLS_RESERVED __BITS(15, 6)
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#define HW_UARTDBGIFLS_RXIFLSEL __BITS(5, 3)
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#define HW_UARTDBGIFLS_TXIFLSEL __BITS(2, 0)
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/*
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* UART Interrupt Mask Set/Clear Register.
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*/
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#define HW_UARTDBGIMSC 0x038
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#define HW_UARTDBGIMSC_UNAVAILABLE __BITS(31, 16)
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#define HW_UARTDBGIMSC_RESERVED __BITS(15, 11)
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#define HW_UARTDBGIMSC_OEIM __BIT(10)
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#define HW_UARTDBGIMSC_BEIM __BIT(9)
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#define HW_UARTDBGIMSC_PEIM __BIT(8)
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#define HW_UARTDBGIMSC_FEIM __BIT(7)
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#define HW_UARTDBGIMSC_RTIM __BIT(6)
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#define HW_UARTDBGIMSC_TXIM __BIT(5)
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#define HW_UARTDBGIMSC_RXIM __BIT(4)
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#define HW_UARTDBGIMSC_DSRMIM __BIT(3)
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#define HW_UARTDBGIMSC_DCDMIM __BIT(2)
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#define HW_UARTDBGIMSC_CTSMIM __BIT(1)
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#define HW_UARTDBGIMSC_RIMIM __BIT(0)
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/*
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* UART Raw Interrupt Status Register.
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*/
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#define HW_UARTDBGRIS 0x03C
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#define HW_UARTDBGRIS_UNAVAILABLE __BITS(31, 16)
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#define HW_UARTDBGRIS_RESERVED __BITS(15, 11)
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#define HW_UARTDBGRIS_OERIS __BIT(10)
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#define HW_UARTDBGRIS_BERIS __BIT(9)
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#define HW_UARTDBGRIS_PERIS __BIT(8)
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#define HW_UARTDBGRIS_FERIS __BIT(7)
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#define HW_UARTDBGRIS_RTRIS __BIT(6)
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#define HW_UARTDBGRIS_TXRIS __BIT(5)
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#define HW_UARTDBGRIS_RXRIS __BIT(4)
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#define HW_UARTDBGRIS_DSRRMIS __BIT(3)
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#define HW_UARTDBGRIS_DCDRMIS __BIT(2)
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#define HW_UARTDBGRIS_CTSRMIS __BIT(1)
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#define HW_UARTDBGRIS_RIRMIS __BIT(0)
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/*
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* UART Masked Interrupt Status Register.
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*/
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#define HW_UARTDBGMIS 0x040
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#define HW_UARTDBGMIS_UNAVAILABLE __BITS(31, 16)
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#define HW_UARTDBGMIS_RESERVED __BITS(15, 11)
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#define HW_UARTDBGMIS_OEMIS __BIT(10)
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#define HW_UARTDBGMIS_BEMIS __BIT(9)
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#define HW_UARTDBGMIS_PEMIS __BIT(8)
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#define HW_UARTDBGMIS_FEMIS __BIT(7)
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#define HW_UARTDBGMIS_RTMIS __BIT(6)
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#define HW_UARTDBGMIS_TXMIS __BIT(5)
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#define HW_UARTDBGMIS_RXMIS __BIT(4)
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#define HW_UARTDBGMIS_DSRMMIS __BIT(3)
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#define HW_UARTDBGMIS_DCDMMIS __BIT(2)
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#define HW_UARTDBGMIS_CTSMMIS __BIT(1)
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#define HW_UARTDBGMIS_RIMMIS __BIT(0)
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/*
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* UART Interrupt Clear Register.
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*/
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#define HW_UARTDBGICR 0x044
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#define HW_UARTDBGICR_UNAVAILABLE __BITS(31, 16)
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#define HW_UARTDBGICR_RESERVED __BITS(15, 11)
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#define HW_UARTDBGICR_OEIC __BIT(10)
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#define HW_UARTDBGICR_BEIC __BIT(9)
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#define HW_UARTDBGICR_PEIC __BIT(8)
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#define HW_UARTDBGICR_FEIC __BIT(7)
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#define HW_UARTDBGICR_RTIC __BIT(6)
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#define HW_UARTDBGICR_TXIC __BIT(5)
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#define HW_UARTDBGICR_RXIC __BIT(4)
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#define HW_UARTDBGICR_DSRMIC __BIT(3)
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#define HW_UARTDBGICR_DCDMIC __BIT(2)
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#define HW_UARTDBGICR_CTSMIC __BIT(1)
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#define HW_UARTDBGICR_RIMIC __BIT(0)
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/*
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* UART DMA Control Register.
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*/
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#define HW_UARTDBGDMACR 0x048
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#define HW_UARTDBGDMACR_UNAVAILABLE __BITS(31, 16)
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#define HW_UARTDBGDMACR_RESERVED __BITS(15, 3)
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#define HW_UARTDBGDMACR_DMAONERR __BIT(2)
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#define HW_UARTDBGDMACR_TXDMAE __BIT(1)
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#define HW_UARTDBGDMACR_RXDMAE __BIT(0)
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#endif /* !_ARM_IMX_IMX23_UARTDBGREG_H_ */
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