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91 lines
2.9 KiB
C
91 lines
2.9 KiB
C
/* $NetBSD: imx51_ccmvar.h,v 1.3 2014/07/25 07:49:56 hkenken Exp $ */
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/*
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* Copyright (c) 2012 Genetec Corporation. All rights reserved.
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* Written by Hashimoto Kenichi for Genetec Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_IMX_IMX51_CCMVAR_H_
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#define _ARM_IMX_IMX51_CCMVAR_H_
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enum imx51_clock {
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IMX51CLK_FPM,
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IMX51CLK_PLL1,
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IMX51CLK_PLL2,
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IMX51CLK_PLL3,
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IMX51CLK_PLL1SW,
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IMX51CLK_PLL2SW,
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IMX51CLK_PLL3SW,
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IMX51CLK_PLL1STEP,
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IMX51CLK_LP_APM,
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IMX51CLK_ARM_ROOT,
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IMX51CLK_MAIN_BUS_CLK_SRC, /* XXX */
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IMX51CLK_MAIN_BUS_CLK,
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IMX51CLK_EMI_SLOW_CLK_ROOT,
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IMX51CLK_ENFC_CLK_ROOT,
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IMX51CLK_AHB_CLK_ROOT,
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IMX51CLK_IPG_CLK_ROOT,
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IMX51CLK_PERCLK_ROOT,
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IMX51CLK_DDR_CLK_ROOT,
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IMX51CLK_ARM_AXI_CLK_ROOT,
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IMX51CLK_ARM_AXI_A_CLK,
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IMX51CLK_ARM_AXI_B_CLK,
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IMX51CLK_IPU_HSP_CLK_ROOT,
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IMX51CLK_CKIL_SYNC_CLK_ROOT,
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IMX51CLK_USBOH3_CLK_ROOT,
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IMX51CLK_ESDHC1_CLK_ROOT,
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IMX51CLK_ESDHC2_CLK_ROOT,
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IMX51CLK_ESDHC3_CLK_ROOT,
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IMX51CLK_ESDHC4_CLK_ROOT,
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IMX51CLK_UART_CLK_ROOT,
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IMX51CLK_SSI1_CLK_ROOT,
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IMX51CLK_SSI2_CLK_ROOT,
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IMX51CLK_SSI_EXT1_CLK_ROOT,
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IMX51CLK_SSI_EXT2_CLK_ROOT,
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IMX51CLK_USB_PHY_CLK_ROOT,
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IMX51CLK_TVE_216_54_CLK_ROOT,
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IMX51CLK_DI_CLK_ROOT,
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IMX51CLK_SPDIF0_CLK_ROOT,
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IMX51CLK_SPDIF1_CLK_ROOT,
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IMX51CLK_CSPI_CLK_ROOT,
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IMX51CLK_WRCK_CLK_ROOT,
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IMX51CLK_LPSR_CLK_ROOT,
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IMX51CLK_PGC_CLK_ROOT,
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#if IMX50
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IMX50CLK_PFD0_CLK_ROOT,
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IMX50CLK_PFD1_CLK_ROOT,
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IMX50CLK_PFD2_CLK_ROOT,
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IMX50CLK_PFD3_CLK_ROOT,
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IMX50CLK_PFD4_CLK_ROOT,
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IMX50CLK_PFD5_CLK_ROOT,
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IMX50CLK_PFD6_CLK_ROOT,
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IMX50CLK_PFD7_CLK_ROOT,
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#endif
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};
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u_int imx51_get_clock(enum imx51_clock);
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void imx51_clk_gating(int, int);
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void imx51_clk_rate(int, int, int);
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#endif /* _ARM_IMX_IMX51_CCMVAR_H_ */
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