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84 lines
2.8 KiB
C
84 lines
2.8 KiB
C
/* $NetBSD: imx6_ccmvar.h,v 1.3 2015/01/09 09:50:46 ryo Exp $ */
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/*
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* Copyright (c) 2012 Genetec Corporation. All rights reserved.
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* Written by Hashimoto Kenichi for Genetec Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_IMX_IMX6_CCMVAR_H_
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#define _ARM_IMX_IMX6_CCMVAR_H_
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enum imx6_clock {
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IMX6CLK_PLL1, /* = PLL_ARM */
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IMX6CLK_PLL2, /* = PLL_SYS = 528_PLL (24MHz * 22) */
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IMX6CLK_PLL3, /* = PLL_USB1 = 480_PLL1 */
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/* (USB/OTG PHY, 480PFD0-480PFD3, 24MHz*20) */
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IMX6CLK_PLL4, /* = PLL_AUDIO */
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IMX6CLK_PLL5, /* = PLL_VIDEO */
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IMX6CLK_PLL6, /* = PLL_ENET (20MHz = 24MHz * 5/6) */
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IMX6CLK_PLL7, /* = PLL_USB2 (USB2 PHY, HOST PHY, 24MHz*20) */
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IMX6CLK_PLL8, /* = PLL_MLB (Media Link Bus) */
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IMX6CLK_PLL2_PFD0,
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IMX6CLK_PLL2_PFD1,
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IMX6CLK_PLL2_PFD2,
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IMX6CLK_PLL3_PFD0,
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IMX6CLK_PLL3_PFD1,
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IMX6CLK_PLL3_PFD2,
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IMX6CLK_PLL3_PFD3,
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IMX6CLK_ARM_ROOT, /* CPU clock of ARM core */
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IMX6CLK_PERIPH,
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IMX6CLK_AHB,
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IMX6CLK_IPG,
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IMX6CLK_AXI,
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IMX6CLK_MMDC_CH0,
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IMX6CLK_MMDC_CH1,
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IMX6CLK_MMDC_CH0_CLK_ROOT,
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IMX6CLK_MMDC_CH1_CLK_ROOT,
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IMX6CLK_USDHC1,
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IMX6CLK_USDHC2,
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IMX6CLK_USDHC3,
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IMX6CLK_USDHC4,
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IMX6CLK_PERCLK,
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IMX6CLK_IPU1_HSP_CLK_ROOT,
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IMX6CLK_IPU2_HSP_CLK_ROOT,
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IMX6CLK_IPU1_DI0_CLK_ROOT,
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IMX6CLK_IPU1_DI1_CLK_ROOT,
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IMX6CLK_LDB_DI0_IPU,
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IMX6CLK_LDB_DI0_SERIAL_CLK_ROOT,
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IMX6CLK_LDB_DI1_IPU,
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IMX6CLK_LDB_DI1_SERIAL_CLK_ROOT,
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};
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uint32_t imx6_get_clock(enum imx6_clock);
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int imx6_set_clock(enum imx6_clock, uint32_t);
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int imx6_pll_power(uint32_t, int);
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uint32_t imx6_ccm_read(uint32_t);
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void imx6_ccm_write(uint32_t, uint32_t);
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#endif /* _ARM_IMX_IMX6_CCMVAR_H_ */
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