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174 lines
4.8 KiB
C
174 lines
4.8 KiB
C
/* $NetBSD: imx6_intr.h,v 1.3 2015/06/01 09:49:36 ryo Exp $ */
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/*-
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_ARM_IMX6_INTR_H_
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#define _ARM_ARM_IMX6_INTR_H_
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#define PIC_MAXSOURCES 256
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#define PIC_MAXMAXSOURCES (256 + 6 * 32)
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#define __HAVE_PIC_PENDING_INTRS /* for imxgpio */
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/*
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* The BCM53xx uses a generic interrupt controller so pull that stuff.
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*/
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#include <arm/cortex/gic_intr.h>
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#include <arm/cortex/a9tmr_intr.h> /* A9 Timer PPIs */
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#define IRQ_IOMUXC 32
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#define IRQ_DAP 33
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#define IRQ_SDMA 34
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#define IRQ_VPU_JPEG 35
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#define IRQ_SNVS_PMIC 36
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#define IRQ_IPU1_ERROR 37
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#define IRQ_IPU1_SYNC 38
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#define IRQ_IPU2_ERROR 39
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#define IRQ_IPU2_SYNC 40
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#define IRQ_GPU3D 41
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#define IRQ_GPU2D_IDLE 42
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#define IRQ_GPU2D 43
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#define IRQ_VPU 44
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#define IRQ_APBH 45
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#define IRQ_EIM 46
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#define IRQ_BCH 47
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#define IRQ_GPMI 48
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#define IRQ_DTCP 49
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#define IRQ_VDOA 50
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#define IRQ_SNVS 51
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#define IRQ_SNVS_SEC 52
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#define IRQ_CSU 53
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#define IRQ_USDHC1 54
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#define IRQ_USDHC2 55
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#define IRQ_USDHC3 56
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#define IRQ_USDHC4 57
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#define IRQ_UART1 58
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#define IRQ_UART2 59
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#define IRQ_UART3 60
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#define IRQ_UART4 61
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#define IRQ_UART5 62
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#define IRQ_ECSPI1 63
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#define IRQ_ECSPI2 64
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#define IRQ_ECSPI3 65
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#define IRQ_ECSPI4 66
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#define IRQ_ECSPI5 67
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#define IRQ_I2C1 68
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#define IRQ_I2C2 69
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#define IRQ_I2C3 70
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#define IRQ_SATA 71
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#define IRQ_USB1 72
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#define IRQ_USB2 73
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#define IRQ_USB3 74
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#define IRQ_USBOTG 75
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#define IRQ_USBPHY0 76
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#define IRQ_USBPHY1 77
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#define IRQ_SSI1 78
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#define IRQ_SSI2 79
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#define IRQ_SSI3 80
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#define IRQ_TEMP 81
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#define IRQ_ASRC 82
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#define IRQ_ESAI 83
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#define IRQ_SPDIF 84
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#define IRQ_MLB 85
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#define IRQ_PMU 86
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#define IRQ_GPT 87
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#define IRQ_EPIT1 88
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#define IRQ_EPIT2 89
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#define IRQ_GPIO7 90
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#define IRQ_GPIO6 91
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#define IRQ_GPIO5 92
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#define IRQ_GPIO4 93
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#define IRQ_GPIO3 94
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#define IRQ_GPIO2 95
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#define IRQ_GPIO1 96
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#define IRQ_GPIO0 97
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#define IRQ_GPIO1L 98
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#define IRQ_GPIO1H 99
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#define IRQ_GPIO2L 100
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#define IRQ_GPIO2H 101
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#define IRQ_GPIO3L 102
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#define IRQ_GPIO3H 103
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#define IRQ_GPIO4L 104
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#define IRQ_GPIO4H 105
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#define IRQ_GPIO5L 106
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#define IRQ_GPIO5H 107
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#define IRQ_GPIO6L 108
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#define IRQ_GPIO6H 109
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#define IRQ_GPIO7L 110
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#define IRQ_GPIO7H 111
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#define IRQ_WDOG1 112
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#define IRQ_WDOG2 113
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#define IRQ_KPP 114
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#define IRQ_PWM1 115
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#define IRQ_PWM2 116
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#define IRQ_PWM3 117
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#define IRQ_PWM4 118
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#define IRQ_CCM1 119
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#define IRQ_CCM2 120
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#define IRQ_GPC 121
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#define IRQ__RSVD122 122
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#define IRQ_SRC 123
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#define IRQ_CPU_L2 124
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#define IRQ_CPU_PARITY 125
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#define IRQ_CPU_PMU 126
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#define IRQ_CPU_CTI 127
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#define IRQ_CPU_WDOG 128
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#define IRQ__RSVD129 129
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#define IRQ__RSVD130 130
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#define IRQ__RSVD131 131
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#define IRQ_MIPI_CSI1 132
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#define IRQ_MIPI_CSI2 133
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#define IRQ_MIPI_DSI 134
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#define IRQ_MIPI_HSI 135
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#define IRQ_SJC 136
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#define IRQ_CAAM0 137
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#define IRQ_CAAM1 138
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#define IRQ__RSVD139 139
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#define IRQ_ASC1 140
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#define IRQ_ASC2 141
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#define IRQ_FLEXCAN1 142
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#define IRQ_FLEXCAN2 143
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#define IRQ__RSVD144 144
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#define IRQ__RSVD145 145
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#define IRQ__RSVD146 146
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#define IRQ_HDMI_MASTER 147
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#define IRQ_HDMI_CEC 148
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#define IRQ_MLB150L 149
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#define IRQ_ENET 150
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#define IRQ_ENET_1588 151
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#define IRQ_PCIE1 152
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#define IRQ_PCIE2 153
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#define IRQ_PCIE3 154
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#define IRQ_PCIE4 155
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#define IRQ_DCIC1 156
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#define IRQ_DCIC2 157
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#define IRQ_MLB150H 158
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#define IRQ_PMU_D 159
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#endif /* _ARM_ARM_IMX6INTR_H_ */
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