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netbsd/sys/arch/arm/imx/imx6_iomuxreg.h
Lionel Sambuc db4f849365 2015/10/10 12:00:00 UTC
2015-10-15 10:25:28 +02:00

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/* $NetBSD: imx6_iomuxreg.h,v 1.2 2015/07/30 08:09:36 ryo Exp $ */
/*
* Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARM_IMX_IMX6_IOMUXREG_H_
#define _ARM_IMX_IMX6_IOMUXREG_H_
#define IOMUX_GPR0 0x00000000
#define IOMUX_GPR1 0x00000004
#define IOMUX_GPR1_CFG_L1_CLK_REMOVAL_EN __BIT(31)
#define IOMUX_GPR1_APP_CLK_REQ_N __BIT(30)
#define IOMUX_GPR1_APP_REQ_EXIT_L1 __BIT(28)
#define IOMUX_GPR1_APP_READY_ENTR_L23 __BIT(27)
#define IOMUX_GPR1_APP_REQ_ENTR_L1 __BIT(26)
#define IOMUX_GPR1_MIPI_COLOR_SW __BIT(25)
#define IOMUX_GPR1_MIPI_DPI_OFF __BIT(24)
#define IOMUX_GPR1_Reserved __BIT(23
#define IOMUX_GPR1_EXC_MON __BIT(22)
#define IOMUX_GPR1_ENET_CLK_SEL __BIT(21)
#define IOMUX_GPR1_MIPI_IPU2_MUX __BIT(20)
#define IOMUX_GPR1_MIPI_IPU1_MUX __BIT(19)
#define IOMUX_GPR1_TEST_POWERDOWN __BIT(18)
#define IOMUX_GPR1_IPU_VPU_MUX __BIT(17)
#define IOMUX_GPR1_REF_SSP_EN __BIT(16)
#define IOMUX_GPR1_USB_EXP_MODE __BIT(15)
#define IOMUX_GPR1_SYS_INT __BIT(14)
#define IOMUX_GPR1_USB_OTG_ID_SEL __BIT(13)
#define IOMUX_GPR1_GINT __BIT(12)
#define IOMUX_GPR1_ADDRS3 __BITS(11, 10)
#define IOMUX_GPR1_ACT_CS3 __BIT(9)
#define IOMUX_GPR1_ADDRS2 __BITS(8, 7)
#define IOMUX_GPR1_ACT_CS2 __BIT(6)
#define IOMUX_GPR1_ADDRS1 __BITS(5, 4)
#define IOMUX_GPR1_ACT_CS1 __BIT(3)
#define IOMUX_GPR1_ADDRS0 __BITS(2, 1)
#define IOMUX_GPR1_ACT_CS0 __BIT(0)
#define IOMUX_GPR2 0x00000008
#define IOMUX_GPR3 0x0000000c
#define IOMUX_GPR4 0x00000010
#define IOMUX_GPR5 0x00000014
#define IOMUX_GPR6 0x00000018
#define IOMUX_GPR7 0x0000001c
#define IOMUX_GPR8 0x00000020
#define IOMUX_GPR8_PCS_TX_SWING_LOW __BITS(31, 25)
#define IOMUX_GPR8_PCS_TX_SWING_FULL __BITS(24, 18)
#define IOMUX_GPR8_PCS_TX_DEEMPH_GEN2_6DB __BITS(17, 12)
#define IOMUX_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB __BITS(11, 6)
#define IOMUX_GPR8_PCS_TX_DEEMPH_GEN1 __BITS(5, 0)
#define IOMUX_GPR9 0x00000024
#define IOMUX_GPR10 0x00000028
#define IOMUX_GPR11 0x0000002c
#define IOMUX_GPR12 0x00000030
#define IOMUX_GPR12_ARMP_IPG_CLK_EN __BIT(27)
#define IOMUX_GPR12_ARMP_AHB_CLK_EN __BIT(26)
#define IOMUX_GPR12_ARMP_ATB_CLK_EN __BIT(25)
#define IOMUX_GPR12_ARMP_APB_CLK_EN __BIT(24)
#define IOMUX_GPR12_PCIE_CTL_7 __BITS(23, 21)
#define IOMUX_GPR12_DIA_STATUS_BUS_SELECT __BITS(20, 17)
#define IOMUX_GPR12_APPS_PM_XMT_TURNOFF __BIT(16)
#define IOMUX_GPR12_DEVICE_TYPE __BITS(15, 12)
#define IOMUX_GPR12_DEVICE_TYPE_PCIE_EP (0 << 12)
#define IOMUX_GPR12_DEVICE_TYPE_PCIE_RC (2 << 12)
#define IOMUX_GPR12_APP_INIT_RST __BIT(11)
#define IOMUX_GPR12_APP_LTSSM_ENABLE __BIT(10)
#define IOMUX_GPR12_APPS_PM_XMT_PME __BIT(9)
#define IOMUX_GPR12_LOS_LEVEL __BITS(8, 4)
#define IOMUX_GPR12_USDHC_DBG_MUX __BITS(3, 2)
#define IOMUX_GPR13 0x00000034
#define IOMUX_GPR13_SDMA_STOP_REQ __BIT(30)
#define IOMUX_GPR13_CAN2_STOP_REQ __BIT(29)
#define IOMUX_GPR13_CAN1_STOP_REQ __BIT(28)
#define IOMUX_GPR13_ENET_STOP_REQ __BIT(27)
#define IOMUX_GPR13_SATA_PHY_8(n) __SHIFTIN(n, __BITS(26, 24))
#define IOMUX_GPR13_SATA_PHY_7(n) __SHIFTIN(n, __BITS(23, 19))
#define IOMUX_GPR13_SATA_PHY_6(n) __SHIFTIN(n, __BITS(18, 16))
#define IOMUX_GPR13_SATA_SPEED(n) __SHIFTIN(n, __BIT(15))
#define IOMUX_GPR13_SATA_PHY_5(n) __SHIFTIN(n, __BIT(14))
#define IOMUX_GPR13_SATA_PHY_4(n) __SHIFTIN(n, __BITS(13, 11))
#define IOMUX_GPR13_SATA_PHY_3(n) __SHIFTIN(n, __BITS(10, 7))
#define IOMUX_GPR13_SATA_PHY_2(n) __SHIFTIN(n, __BITS(6, 2))
#define IOMUX_GPR13_SATA_PHY_1(n) __SHIFTIN(n, __BIT(1))
#define IOMUX_GPR13_SATA_PHY_0(n) __SHIFTIN(n, __BIT(0))
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 0x0000004c
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 0x00000050
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 0x00000054
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC 0x00000058
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0 0x0000005c
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1 0x00000060
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2 0x00000064
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3 0x00000068
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL 0x0000006c
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0 0x00000070
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL 0x00000074
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1 0x00000078
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2 0x0000007c
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3 0x00000080
#define IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC 0x00000084
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25 0x00000088
#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_B 0x0000008c
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16 0x00000090
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17 0x00000094
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18 0x00000098
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19 0x0000009c
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20 0x000000a0
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x000000a4
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22 0x000000a8
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23 0x000000ac
#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_B 0x000000b0
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24 0x000000b4
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25 0x000000b8
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26 0x000000bc
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27 0x000000c0
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x000000c4
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29 0x000000c8
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30 0x000000cc
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31 0x000000d0
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24 0x000000d4
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23 0x000000d8
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22 0x000000dc
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21 0x000000e0
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20 0x000000e4
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19 0x000000e8
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18 0x000000ec
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17 0x000000f0
#define IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16 0x000000f4
#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_B 0x000000f8
#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_B 0x000000fc
#define IOMUXC_SW_MUX_CTL_PAD_EIM_OE_B 0x00000100
#define IOMUXC_SW_MUX_CTL_PAD_EIM_RW 0x00000104
#define IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_B 0x00000108
#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_B 0x0000010c
#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_B 0x00000110
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD00 0x00000114
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD01 0x00000118
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD02 0x0000011c
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD03 0x00000120
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD04 0x00000124
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD05 0x00000128
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD06 0x0000012c
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD07 0x00000130
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD08 0x00000134
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD09 0x00000138
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD10 0x0000013c
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD11 0x00000140
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD12 0x00000144
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD13 0x00000148
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD14 0x0000014c
#define IOMUXC_SW_MUX_CTL_PAD_EIM_AD15 0x00000150
#define IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_B 0x00000154
#define IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK 0x00000158
#define IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK 0x0000015c
#define IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15 0x00000160
#define IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02 0x00000164
#define IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03 0x00000168
#define IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04 0x0000016c
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00 0x00000170
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01 0x00000174
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02 0x00000178
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03 0x0000017c
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04 0x00000180
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05 0x00000184
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06 0x00000188
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07 0x0000018c
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08 0x00000190
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09 0x00000194
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10 0x00000198
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11 0x0000019c
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12 0x000001a0
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13 0x000001a4
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14 0x000001a8
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15 0x000001ac
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16 0x000001b0
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17 0x000001b4
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18 0x000001b8
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19 0x000001bc
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20 0x000001c0
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21 0x000001c4
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22 0x000001c8
#define IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23 0x000001cc
#define IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO 0x000001d0
#define IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK 0x000001d4
#define IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER 0x000001d8
#define IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV 0x000001dc
#define IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1 0x000001e0
#define IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0 0x000001e4
#define IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN 0x000001e8
#define IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1 0x000001ec
#define IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0 0x000001f0
#define IOMUXC_SW_MUX_CTL_PAD_ENET_MDC 0x000001f4
#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0 0x000001f8
#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0 0x000001fc
#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1 0x00000200
#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 0x00000204
#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2 0x00000208
#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2 0x0000020c
#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3 0x00000210
#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3 0x00000214
#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 0x00000218
#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4 0x0000021c
#define IOMUXC_SW_MUX_CTL_PAD_GPIO00 0x00000220
#define IOMUXC_SW_MUX_CTL_PAD_GPIO01 0x00000224
#define IOMUXC_SW_MUX_CTL_PAD_GPIO09 0x00000228
#define IOMUXC_SW_MUX_CTL_PAD_GPIO03 0x0000022c
#define IOMUXC_SW_MUX_CTL_PAD_GPIO06 0x00000230
#define IOMUXC_SW_MUX_CTL_PAD_GPIO02 0x00000234
#define IOMUXC_SW_MUX_CTL_PAD_GPIO04 0x00000238
#define IOMUXC_SW_MUX_CTL_PAD_GPIO05 0x0000023c
#define IOMUXC_SW_MUX_CTL_PAD_GPIO07 0x00000240
#define IOMUXC_SW_MUX_CTL_PAD_GPIO08 0x00000244
#define IOMUXC_SW_MUX_CTL_PAD_GPIO16 0x00000248
#define IOMUXC_SW_MUX_CTL_PAD_GPIO17 0x0000024c
#define IOMUXC_SW_MUX_CTL_PAD_GPIO18 0x00000250
#define IOMUXC_SW_MUX_CTL_PAD_GPIO19 0x00000254
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK 0x00000258
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC 0x0000025c
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN 0x00000260
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC 0x00000264
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04 0x00000268
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05 0x0000026c
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06 0x00000270
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07 0x00000274
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08 0x00000278
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09 0x0000027c
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10 0x00000280
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11 0x00000284
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12 0x00000288
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13 0x0000028c
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14 0x00000290
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15 0x00000294
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16 0x00000298
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17 0x0000029c
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18 0x000002a0
#define IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19 0x000002a4
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 0x000002a8
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 0x000002ac
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5 0x000002b0
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4 0x000002b4
#define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD 0x000002b8
#define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK 0x000002bc
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 0x000002c0
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 0x000002c4
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2 0x000002c8
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3 0x000002cc
#define IOMUXC_SW_MUX_CTL_PAD_SD3_RESET 0x000002d0
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE 0x000002d4
#define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE 0x000002d8
#define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B 0x000002dc
#define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B 0x000002e0
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B 0x000002e4
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B 0x000002e8
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B 0x000002ec
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B 0x000002f0
#define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD 0x000002f4
#define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK 0x000002f8
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 0x000002fc
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 0x00000300
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 0x00000304
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 0x00000308
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 0x0000030c
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 0x00000310
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 0x00000314
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 0x00000318
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0 0x0000031c
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1 0x00000320
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2 0x00000324
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3 0x00000328
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4 0x0000032c
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5 0x00000330
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6 0x00000334
#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7 0x00000338
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 0x0000033c
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 0x00000340
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 0x00000344
#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD 0x00000348
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 0x0000034c
#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK 0x00000350
#define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK 0x00000354
#define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD 0x00000358
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 0x0000035c
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 0x00000360
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 0x00000364
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 0x00000368
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC 0x0000036c
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0 0x00000370
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1 0x00000374
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2 0x00000378
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3 0x0000037c
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL 0x00000380
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0 0x00000384
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL 0x00000388
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1 0x0000038c
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2 0x00000390
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3 0x00000394
#define IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC 0x00000398
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25 0x0000039c
#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_B 0x000003a0
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16 0x000003a4
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17 0x000003a8
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18 0x000003ac
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19 0x000003b0
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20 0x000003b4
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 0x000003b8
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22 0x000003bc
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23 0x000003c0
#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_B 0x000003c4
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24 0x000003c8
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25 0x000003cc
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26 0x000003d0
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27 0x000003d4
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 0x000003d8
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29 0x000003dc
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30 0x000003e0
#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31 0x000003e4
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24 0x000003e8
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23 0x000003ec
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22 0x000003f0
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21 0x000003f4
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20 0x000003f8
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19 0x000003fc
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18 0x00000400
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17 0x00000404
#define IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16 0x00000408
#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_B 0x0000040c
#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_B 0x00000410
#define IOMUXC_SW_PAD_CTL_PAD_EIM_OE_B 0x00000414
#define IOMUXC_SW_PAD_CTL_PAD_EIM_RW 0x00000418
#define IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_B 0x0000041c
#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_B 0x00000420
#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_B 0x00000424
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD00 0x00000428
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD01 0x0000042c
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD02 0x00000430
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD03 0x00000434
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD04 0x00000438
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD05 0x0000043c
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD06 0x00000440
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD07 0x00000444
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD08 0x00000448
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD09 0x0000044c
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD10 0x00000450
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD11 0x00000454
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD12 0x00000458
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD13 0x0000045c
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD14 0x00000460
#define IOMUXC_SW_PAD_CTL_PAD_EIM_AD15 0x00000464
#define IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_B 0x00000468
#define IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK 0x0000046c
#define IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK 0x00000470
#define IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15 0x00000474
#define IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02 0x00000478
#define IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03 0x0000047c
#define IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04 0x00000480
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00 0x00000484
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01 0x00000488
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02 0x0000048c
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03 0x00000490
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04 0x00000494
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05 0x00000498
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06 0x0000049c
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07 0x000004a0
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08 0x000004a4
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09 0x000004a8
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10 0x000004ac
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11 0x000004b0
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12 0x000004b4
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13 0x000004b8
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14 0x000004bc
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15 0x000004c0
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16 0x000004c4
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17 0x000004c8
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18 0x000004cc
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19 0x000004d0
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20 0x000004d4
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21 0x000004d8
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22 0x000004dc
#define IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23 0x000004e0
#define IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO 0x000004e4
#define IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK 0x000004e8
#define IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER 0x000004ec
#define IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV 0x000004f0
#define IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1 0x000004f4
#define IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0 0x000004f8
#define IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN 0x000004fc
#define IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1 0x00000500
#define IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0 0x00000504
#define IOMUXC_SW_PAD_CTL_PAD_ENET_MDC 0x00000508
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P 0x0000050c
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 0x00000510
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 0x00000514
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P 0x00000518
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P 0x0000051c
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 0x00000520
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P 0x00000524
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 0x00000528
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 0x0000052c
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 0x00000530
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 0x00000534
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 0x00000538
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 0x0000053c
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 0x00000540
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 0x00000544
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 0x00000548
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 0x0000054c
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 0x00000550
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 0x00000554
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 0x00000558
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 0x0000055c
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 0x00000560
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 0x00000564
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 0x00000568
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B 0x0000056c
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B 0x00000570
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B 0x00000574
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B 0x00000578
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET 0x0000057c
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 0x00000580
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 0x00000584
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P 0x00000588
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 0x0000058c
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 0x00000590
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P 0x00000594
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 0x00000598
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 0x0000059c
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 0x000005a0
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B 0x000005a4
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P 0x000005a8
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x000005ac
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P 0x000005b0
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x000005b4
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P 0x000005b8
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 0x000005bc
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P 0x000005c0
#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 0x000005c4
#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0 0x000005c8
#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0 0x000005cc
#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1 0x000005d0
#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1 0x000005d4
#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2 0x000005d8
#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2 0x000005dc
#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3 0x000005e0
#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3 0x000005e4
#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4 0x000005e8
#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4 0x000005ec
#define IOMUXC_SW_PAD_CTL_PAD_GPIO00 0x000005f0
#define IOMUXC_SW_PAD_CTL_PAD_GPIO01 0x000005f4
#define IOMUXC_SW_PAD_CTL_PAD_GPIO09 0x000005f8
#define IOMUXC_SW_PAD_CTL_PAD_GPIO03 0x000005fc
#define IOMUXC_SW_PAD_CTL_PAD_GPIO06 0x00000600
#define IOMUXC_SW_PAD_CTL_PAD_GPIO02 0x00000604
#define IOMUXC_SW_PAD_CTL_PAD_GPIO04 0x00000608
#define IOMUXC_SW_PAD_CTL_PAD_GPIO05 0x0000060c
#define IOMUXC_SW_PAD_CTL_PAD_GPIO07 0x00000610
#define IOMUXC_SW_PAD_CTL_PAD_GPIO08 0x00000614
#define IOMUXC_SW_PAD_CTL_PAD_GPIO16 0x00000618
#define IOMUXC_SW_PAD_CTL_PAD_GPIO17 0x0000061c
#define IOMUXC_SW_PAD_CTL_PAD_GPIO18 0x00000620
#define IOMUXC_SW_PAD_CTL_PAD_GPIO19 0x00000624
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK 0x00000628
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC 0x0000062c
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN 0x00000630
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC 0x00000634
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04 0x00000638
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05 0x0000063c
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06 0x00000640
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07 0x00000644
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08 0x00000648
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09 0x0000064c
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10 0x00000650
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11 0x00000654
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12 0x00000658
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13 0x0000065c
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14 0x00000660
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15 0x00000664
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16 0x00000668
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17 0x0000066c
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18 0x00000670
#define IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19 0x00000674
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS 0x00000678
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD 0x0000067c
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB 0x00000680
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI 0x00000684
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK 0x00000688
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO 0x0000068c
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7 0x00000690
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6 0x00000694
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5 0x00000698
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4 0x0000069c
#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD 0x000006a0
#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK 0x000006a4
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0 0x000006a8
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1 0x000006ac
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2 0x000006b0
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3 0x000006b4
#define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET 0x000006b8
#define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE 0x000006bc
#define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE 0x000006c0
#define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B 0x000006c4
#define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B 0x000006c8
#define IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B 0x000006cc
#define IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B 0x000006d0
#define IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B 0x000006d4
#define IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B 0x000006d8
#define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD 0x000006dc
#define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK 0x000006e0
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 0x000006e4
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 0x000006e8
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 0x000006ec
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 0x000006f0
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 0x000006f4
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 0x000006f8
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 0x000006fc
#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 0x00000700
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0 0x00000704
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1 0x00000708
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2 0x0000070c
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3 0x00000710
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4 0x00000714
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5 0x00000718
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6 0x0000071c
#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7 0x00000720
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 0x00000724
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 0x00000728
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 0x0000072c
#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD 0x00000730
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 0x00000734
#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK 0x00000738
#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK 0x0000073c
#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD 0x00000740
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 0x00000744
#define IOMUXC_SW_PAD_CTL_GRP_B7DS 0x00000748
#define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x0000074c
#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x00000750
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0 0x00000754
#define IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x00000758
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1 0x0000075c
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2 0x00000760
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3 0x00000764
#define IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x00000768
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4 0x0000076c
#define IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x00000770
#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x00000774
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5 0x00000778
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6 0x0000077c
#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7 0x00000780
#define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x00000784
#define IOMUXC_SW_PAD_CTL_GRP_B1DS 0x00000788
#define IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x0000078c
#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII 0x00000790
#define IOMUXC_SW_PAD_CTL_GRP_B2DS 0x00000794
#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 0x00000798
#define IOMUXC_SW_PAD_CTL_GRP_B3DS 0x0000079c
#define IOMUXC_SW_PAD_CTL_GRP_B4DS 0x000007a0
#define IOMUXC_SW_PAD_CTL_GRP_B5DS 0x000007a4
#define IOMUXC_SW_PAD_CTL_GRP_B6DS 0x000007a8
#define IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM 0x000007ac
#define IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT 0x000007b0
#define IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT 0x000007b4
#define IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT 0x000007b8
#define IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT 0x000007bc
#define IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT 0x000007c0
#define IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT 0x000007c4
#define IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT 0x000007c8
#define IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT 0x000007cc
#define IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT 0x000007d0
#define IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT 0x000007d4
#define IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT 0x000007d8
#define IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT 0x000007dc
#define IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT 0x000007e0
#define IOMUXC_FLEXCAN1_RX_SELECT_INPUT 0x000007e4
#define IOMUXC_FLEXCAN2_RX_SELECT_INPUT 0x000007e8
#define IOMUXC_CCM_PMIC_READY_SELECT_INPUT 0x000007f0
#define IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT 0x000007f4
#define IOMUXC_ECSPI1_MISO_SELECT_INPUT 0x000007f8
#define IOMUXC_ECSPI1_MOSI_SELECT_INPUT 0x000007fc
#define IOMUXC_ECSPI1_SS0_SELECT_INPUT 0x00000800
#define IOMUXC_ECSPI1_SS1_SELECT_INPUT 0x00000804
#define IOMUXC_ECSPI1_SS2_SELECT_INPUT 0x00000808
#define IOMUXC_ECSPI1_SS3_SELECT_INPUT 0x0000080c
#define IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT 0x00000810
#define IOMUXC_ECSPI2_MISO_SELECT_INPUT 0x00000814
#define IOMUXC_ECSPI2_MOSI_SELECT_INPUT 0x00000818
#define IOMUXC_ECSPI2_SS0_SELECT_INPUT 0x0000081c
#define IOMUXC_ECSPI2_SS1_SELECT_INPUT 0x00000820
#define IOMUXC_ECSPI4_SS0_SELECT_INPUT 0x00000824
#define IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT 0x00000828
#define IOMUXC_ECSPI5_MISO_SELECT_INPUT 0x0000082c
#define IOMUXC_ECSPI5_MOSI_SELECT_INPUT 0x00000830
#define IOMUXC_ECSPI5_SS0_SELECT_INPUT 0x00000834
#define IOMUXC_ECSPI5_SS1_SELECT_INPUT 0x00000838
#define IOMUXC_ENET_REF_CLK_SELECT_INPUT 0x0000083c
#define IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT 0x00000840
#define IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT 0x00000844
#define IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT 0x00000848
#define IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT 0x0000084c
#define IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT 0x00000850
#define IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT 0x00000854
#define IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT 0x00000858
#define IOMUXC_ESAI_RX_FS_SELECT_INPUT 0x0000085c
#define IOMUXC_ESAI_TX_FS_SELECT_INPUT 0x00000860
#define IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT 0x00000864
#define IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT 0x00000868
#define IOMUXC_ESAI_RX_CLK_SELECT_INPUT 0x0000086c
#define IOMUXC_ESAI_TX_CLK_SELECT_INPUT 0x00000870
#define IOMUXC_ESAI_SDO0_SELECT_INPUT 0x00000874
#define IOMUXC_ESAI_SDO1_SELECT_INPUT 0x00000878
#define IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT 0x0000087c
#define IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT 0x00000880
#define IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT 0x00000884
#define IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT 0x00000888
#define IOMUXC_HDMI_ICECIN_SELECT_INPUT 0x0000088c
#define IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT 0x00000890
#define IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT 0x00000894
#define IOMUXC_I2C1_SCL_IN_SELECT_INPUT 0x00000898
#define IOMUXC_I2C1_SDA_IN_SELECT_INPUT 0x0000089c
#define IOMUXC_I2C2_SCL_IN_SELECT_INPUT 0x000008a0
#define IOMUXC_I2C2_SDA_IN_SELECT_INPUT 0x000008a4
#define IOMUXC_I2C3_SCL_IN_SELECT_INPUT 0x000008a8
#define IOMUXC_I2C3_SDA_IN_SELECT_INPUT 0x000008ac
#define IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT 0x000008b0
#define IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT 0x000008b4
#define IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT 0x000008b8
#define IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT 0x000008bc
#define IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT 0x000008c0
#define IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT 0x000008c4
#define IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT 0x000008c8
#define IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT 0x000008cc
#define IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT 0x000008d0
#define IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT 0x000008d4
#define IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT 0x000008d8
#define IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT 0x000008dc
#define IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT 0x000008e0
#define IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT 0x000008e4
#define IOMUXC_KEY_COL5_SELECT_INPUT 0x000008e8
#define IOMUXC_KEY_COL6_SELECT_INPUT 0x000008ec
#define IOMUXC_KEY_COL7_SELECT_INPUT 0x000008f0
#define IOMUXC_KEY_ROW5_SELECT_INPUT 0x000008f4
#define IOMUXC_KEY_ROW6_SELECT_INPUT 0x000008f8
#define IOMUXC_KEY_ROW7_SELECT_INPUT 0x000008fc
#define IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT 0x00000900
#define IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT 0x00000904
#define IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT 0x00000908
#define IOMUXC_SDMA_EVENTS14_SELECT_INPUT 0x0000090c
#define IOMUXC_SDMA_EVENTS15_SELECT_INPUT 0x00000910
#define IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT 0x00000914
#define IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT 0x00000918
#define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT 0x0000091c
#define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x00000920
#define IOMUXC_UART2_UART_RTS_B_SELECT_INPUT 0x00000924
#define IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT 0x00000928
#define IOMUXC_UART3_UART_RTS_B_SELECT_INPUT 0x0000092c
#define IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT 0x00000930
#define IOMUXC_UART4_UART_RTS_B_SELECT_INPUT 0x00000934
#define IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT 0x00000938
#define IOMUXC_UART5_UART_RTS_B_SELECT_INPUT 0x0000093c
#define IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT 0x00000940
#define IOMUXC_USB_OTG_OC_SELECT_INPUT 0x00000944
#define IOMUXC_USB_H1_OC_SELECT_INPUT 0x00000948
/* IOMUXC_SW_MUX_CTL_PAD_xxx */
#define IOMUX_CONFIG_SION __BIT(4)
#define IOMUX_CONFIG_ALT0 0
#define IOMUX_CONFIG_ALT1 1
#define IOMUX_CONFIG_ALT2 2
#define IOMUX_CONFIG_ALT3 3
#define IOMUX_CONFIG_ALT4 4
#define IOMUX_CONFIG_ALT5 5
#define IOMUX_CONFIG_ALT6 6
#define IOMUX_CONFIG_ALT7 7
/* IOMUXC_SW_PAD_CTL_PAD_xxx */
#define PAD_CTL_DDR_SEL_MASK __BITS(19, 18)
#define PAD_CTL_DDR_SEL_0 __SHIFTIN(0, PAD_CTL_DDR_SEL_MASK)
#define PAD_CTL_DDR_SEL_1 __SHIFTIN(1, PAD_CTL_DDR_SEL_MASK)
#define PAD_CTL_DDR_SEL_2 __SHIFTIN(2, PAD_CTL_DDR_SEL_MASK)
#define PAD_CTL_DDR_SEL_3 __SHIFTIN(3, PAD_CTL_DDR_SEL_MASK)
#define PAD_CTL_HYS __BIT(16)
#define PAD_CTL_PUS_MASK __BITS(15, 14)
#define PAD_CTL_PUS_100K_PD __SHIFTIN(0x0, PAD_CTL_PUS_MASK)
#define PAD_CTL_PUS_47K_PU __SHIFTIN(0x1, PAD_CTL_PUS_MASK)
#define PAD_CTL_PUS_100K_PU __SHIFTIN(0x2, PAD_CTL_PUS_MASK)
#define PAD_CTL_PUS_22K_PU __SHIFTIN(0x3, PAD_CTL_PUS_MASK)
#define PAD_CTL_PUE __BIT(13)
#define PAD_CTL_PKE __BIT(12)
#define PAD_CTL_PULL (PAD_CTL_PKE|PAD_CTL_PUE)
#define PAD_CTL_KEEPER (PAD_CTL_PKE|0)
#define PAD_CTL_ODE __BIT(11)
#define PAD_CTL_ODT __BITS(10, 8)
#define PAD_CTL_SPEED_MASK __BITS(7, 6)
#define PAD_CTL_SPEED_RESERVED0 __SHIFTIN(0, PAD_CTL_SPEED_MASK)
#define PAD_CTL_SPEED_50MHZ __SHIFTIN(1, PAD_CTL_SPEED_MASK)
#define PAD_CTL_SPEED_100MHZ __SHIFTIN(2, PAD_CTL_SPEED_MASK)
#define PAD_CTL_SPEED_200MHZ __SHIFTIN(3, PAD_CTL_SPEED_MASK)
#define PAD_CTL_DSE_MASK __BITS(5, 3)
#define PAD_CTL_DSE_HIZ __SHIFTIN(0x0, PAD_CTL_DSE_MASK)
#define PAD_CTL_DSE_290OHM __SHIFTIN(0x1, PAD_CTL_DSE_MASK)
#define PAD_CTL_DSE_240OHM __SHIFTIN(0x1, PAD_CTL_DSE_MASK)
#define PAD_CTL_DSE_121OHM __SHIFTIN(0x2, PAD_CTL_DSE_MASK)
#define PAD_CTL_DSE_120OHM __SHIFTIN(0x2, PAD_CTL_DSE_MASK)
#define PAD_CTL_DSE_80OHM __SHIFTIN(0x3, PAD_CTL_DSE_MASK)
#define PAD_CTL_DSE_76OHM __SHIFTIN(0x3, PAD_CTL_DSE_MASK)
#define PAD_CTL_DSE_60OHM __SHIFTIN(0x4, PAD_CTL_DSE_MASK)
#define PAD_CTL_DSE_48OHM __SHIFTIN(0x5, PAD_CTL_DSE_MASK)
#define PAD_CTL_DSE_47OHM __SHIFTIN(0x4, PAD_CTL_DSE_MASK)
#define PAD_CTL_DSE_45OHM __SHIFTIN(0x5, PAD_CTL_DSE_MASK)
#define PAD_CTL_DSE_40OHM __SHIFTIN(0x6, PAD_CTL_DSE_MASK)
#define PAD_CTL_DSE_37OHM __SHIFTIN(0x6, PAD_CTL_DSE_MASK)
#define PAD_CTL_DSE_34OHM __SHIFTIN(0x7, PAD_CTL_DSE_MASK)
#define PAD_CTL_DSE_31OHM __SHIFTIN(0x7, PAD_CTL_DSE_MASK)
#define PAD_CTL_SRE __BIT(0)
#define PAD_CTL_SRE_SLOW 0
#define PAD_CTL_SRE_FAST PAD_CTL_SRE
/* IOMUXC_SW_PAD_CTL_PAD_xxx */
#define INPUT_DAISY_0 0
#define INPUT_DAISY_1 1
#define INPUT_DAISY_2 2
#define INPUT_DAISY_3 3
#define INPUT_DAISY_4 4
#define INPUT_DAISY_5 5
#define INPUT_DAISY_6 6
#define INPUT_DAISY_7 7
/*
* IOMUX index macro
*/
#define IOMUX_PIN_TO_MUX_ADDRESS(pin) (((pin) >> 16) & 0xffff)
#define IOMUX_PIN_TO_PAD_ADDRESS(pin) (((pin) >> 0) & 0xffff)
#define IOMUX_MUX_NONE 0xffff
#define IOMUX_PAD_NONE 0xffff
#define IOMUX_PIN(mux_adr, pad_adr) \
(((mux_adr) << 16) | (((pad_adr) << 0)))
#define MUX_PIN(name) \
IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_##name, \
IOMUXC_SW_PAD_CTL_PAD_##name)
#endif /* _ARM_IMX_IMX6_IOMUXREG_H_ */
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