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221 lines
6.9 KiB
C
221 lines
6.9 KiB
C
/* $NetBSD: imx6_reg.h,v 1.4 2015/03/27 05:31:23 hkenken Exp $ */
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/*-
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_IMX_IMX6_REG_H_
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#define _ARM_IMX_IMX6_REG_H_
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#define IMX6_IOREG_PBASE IMX6_AIPS1_BASE
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#define IMX6_IOREG_SIZE (IMX6_AIPS1_SIZE + IMX6_AIPS2_SIZE)
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#define IMX6_ARMCORE_PBASE IMX6_MPCORE_BASE
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#define IMX6_ARMCORE_SIZE IMX6_MPCORE_SIZE
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#define IMX6_IO_SIZE (IMX6_IOREG_SIZE + IMX6_ARMCORE_SIZE)
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#define ARMCORE_SCU_BASE 0x00000000
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#define ARMCORE_L2C_BASE 0x00002000
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#define IMX6_MEM_BASE 0x10000000
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#define IMX6_MEM_SIZE 0xF0000000
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#define IMX6_CS0_BASE 0x08000000
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#define IMX6_CS0_SIZE 0x08000000
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#define IMX6_IPU2_BASE 0x02c00000
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#define IMX6_IPU2_SIZE 0x00400000
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#define IMX6_IPU1_BASE 0x02800000
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#define IMX6_IPU1_SIZE 0x00400000
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#define IMX6_HSI_BASE 0x02208000
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#define IMX6_HSI_SIZE 0x00004000
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#define IMX6_OPENVG_BASE 0x02204000
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#define IMX6_OPENVG_SIZE 0x00004000
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#define IMX6_SATA_BASE 0x02200000
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#define IMX6_SATA_SIZE 0x00004000
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#define IMX6_AIPS2_BASE 0x02100000
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#define IMX6_AIPS2_SIZE 0x00100000
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#define IMX6_AIPS1_BASE 0x02000000
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#define IMX6_AIPS1_SIZE 0x00100000
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#define IMX6_PCIE_BASE 0x01ffc000
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#define IMX6_PCIE_SIZE 0x00004000
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#define IMX6_PCIEMEM_BASE 0x01000000
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#define IMX6_PCIEMEM_SIZE 0x00ffc000
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#define IMX6_GPV1_BASE 0x00c00000
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#define IMX6_GPV1_SIZE 0x00100000
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#define IMX6_GPV0_BASE 0x00b00000
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#define IMX6_GPV0_SIZE 0x00100000
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#define IMX6_L2CC_BASE 0x00a02000
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#define IMX6_L2CC_SIZE 0x00001000
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#define IMX6_MPCORE_BASE 0x00a00000
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#define IMX6_MPCORE_SIZE 0x00100000
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#define IMX6_OCRAM1_BASE 0x00940000
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#define IMX6_OCRAM1_SIZE 0x000c0000
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#define IMX6_OCRAM0_BASE 0x00900000
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#define IMX6_OCRAM0_SIZE 0x00040000
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#define IMX6_GPV4_BASE 0x00800000
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#define IMX6_GPV4_SIZE 0x00100000
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#define IMX6_GPV3_BASE 0x00300000
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#define IMX6_GPV3_SIZE 0x00100000
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#define IMX6_GPV2_BASE 0x00200000
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#define IMX6_GPV2_SIZE 0x00100000
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#define IMX6_DTPC_BASE 0x00138000
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#define IMX6_DTPC_SIZE 0x00004000
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#define IMX6_GPU2D_BASE 0x00134000
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#define IMX6_GPU2D_SIZE 0x00004000
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#define IMX6_GPU3D_BASE 0x00130000
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#define IMX6_GPU3D_SIZE 0x00004000
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#define IMX6_HDMI_BASE 0x00120000
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#define IMX6_HDMI_SIZE 0x00009000
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#define IMX6_APBHDMA_BASE 0x00110000
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#define IMX6_APBHDMA_SIZE 0x00002000
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#define IMX6_GPMI_BASE 0x00112000
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#define IMX6_GPMI_SIZE 0x00002000
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#define IMX6_BCH_BASE 0x00114000
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#define IMX6_BCH_SIZE 0x00004000
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#define IMX6_CAAM_BASE 0x00100000
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#define IMX6_CAAM_SIZE 0x00004000
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#define IMX6_ROMCP_BASE 0x00000000
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#define IMX6_ROMCP_SIZE 0x00018000
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#define AIPS1_SDMA_BASE 0x000ec000
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#define AIPS1_DCIC2_BASE 0x000e8000
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#define AIPS1_DCIC1_BASE 0x000e4000
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#define AIPS1_IOMUXC_BASE 0x000e0000
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#define AIPS1_IOMUXC_SIZE 0x00001000
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#define AIPS1_GPC_BASE 0x000dc000
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#define AIPS1_SRC_BASE 0x000d8000
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#define AIPS1_EPIT2_BASE 0x000d4000
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#define AIPS1_EPIT1_BASE 0x000d0000
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#define AIPS1_EPIT_SIZE 0x00000020
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#define AIPS1_SNVS_BASE 0x000cc000
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#define AIPS1_SNVS_SIZE 0x00000c00
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#define AIPS1_USBPHY2_BASE 0x000ca000
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#define AIPS1_USBPHY1_BASE 0x000c9000
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#define AIPS1_ANATOP_DIG_BASE 0x000c8000
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#define AIPS1_CCM_BASE 0x000c4000
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#define AIPS1_WDOG2_BASE 0x000c0000
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#define AIPS1_WDOG1_BASE 0x000bc000
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#define AIPS1_WDOG_SIZE 0x00000010
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#define AIPS1_KPP_BASE 0x000b8000
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#define AIPS1_GPIO7_BASE 0x000b4000
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#define AIPS1_GPIO6_BASE 0x000b0000
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#define AIPS1_GPIO5_BASE 0x000ac000
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#define AIPS1_GPIO4_BASE 0x000a8000
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#define AIPS1_GPIO3_BASE 0x000a4000
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#define AIPS1_GPIO2_BASE 0x000a0000
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#define AIPS1_GPIO1_BASE 0x0009c000
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#define GPIO_NGROUPS 7
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#define AIPS1_GPT_BASE 0x00098000
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#define AIPS1_CAN2_BASE 0x00094000
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#define AIPS1_CAN1_BASE 0x00090000
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#define AIPS1_PWM4_BASE 0x0008c000
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#define AIPS1_PWM3_BASE 0x00088000
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#define AIPS1_PWM2_BASE 0x00084000
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#define AIPS1_PWM1_BASE 0x00080000
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#define AIPS1_CONFIG_BASE 0x0007c000
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#define AIPS1_VPU_BASE 0x00040000
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#define AIPS1_SPBA_BASE 0x0003c000
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#define AIPS1_ASRC_BASE 0x00034000
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#define AIPS1_SSI3_BASE 0x00030000
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#define AIPS1_SSI2_BASE 0x0002c000
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#define AIPS1_SSI1_BASE 0x00028000
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#define AIPS1_ESAI_BASE 0x00024000
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#define AIPS1_UART1_BASE 0x00020000
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#define AIPS1_ECSPI5_BASE 0x00018000
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#define AIPS1_ECSPI4_BASE 0x00014000
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#define AIPS1_ECSPI3_BASE 0x00010000
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#define AIPS1_ECSPI2_BASE 0x0000c000
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#define AIPS1_ECSPI1_BASE 0x00008000
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#define AIPS1_SPDIF_BASE 0x00004000
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#define AIPS2_UART5_BASE 0x000f4000
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#define AIPS2_UART4_BASE 0x000f0000
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#define AIPS2_UART3_BASE 0x000ec000
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#define AIPS2_UART2_BASE 0x000e8000
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#define AIPS2_VDOA_BASE 0x000e3000
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#define AIPS2_MIPIDSI_BASE 0x000e0000
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#define AIPS2_MIPICSI_BASE 0x000dc000
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#define AIPS2_AUDMUX_BASE 0x000d8000
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#define AIPS2_TZASC2_BASE 0x000d4000
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#define AIPS2_TZASC1_BASE 0x000d0000
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#define AIPS2_CSU_BASE 0x000c0000
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#define AIPS2_OCOTP_CTRL_BASE 0x000bc000
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#define AIPS2_OCOTP_CTRL_SIZE 0x00000700
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#define AIPS2_WEIM_BASE 0x000b8000
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#define AIPS2_MMDC2_BASE 0x000b4000
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#define AIPS2_MMDC1_BASE 0x000b0000
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#define AIPS2_ROMCP_BASE 0x000ac000
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#define AIPS2_I2C3_BASE 0x000a8000
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#define AIPS2_I2C2_BASE 0x000a4000
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#define AIPS2_I2C1_BASE 0x000a0000
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#define I2C_SIZE 0x4000
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#define AIPS2_USDHC4_BASE 0x0009c000
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#define AIPS2_USDHC3_BASE 0x00098000
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#define AIPS2_USDHC2_BASE 0x00094000
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#define AIPS2_USDHC1_BASE 0x00090000
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#define AIPS2_USDHC_SIZE 0x000000d0
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#define AIPS2_MLB150_BASE 0x0008c000
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#define AIPS2_ENET_BASE 0x00088000
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#define AIPS2_ENET_SIZE 0x00000800
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#define AIPS2_USBOH_BASE 0x00084000
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#define AIPS2_USBOH_SIZE 0x00000820
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#define AIPS2_CONFIG_BASE 0x0007c000
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#define AIPS2_DAP_BASE 0x00040000
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#define AIPS2_CAAM_BASE 0x00000000
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#endif /* _ARM_IMX_IMX6_REG_H_ */
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