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94 lines
3.8 KiB
C
94 lines
3.8 KiB
C
/* $NetBSD: imxcspireg.h,v 1.1 2014/03/22 09:28:08 hkenken Exp $ */
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/*
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* Copyright (c) 2014 Genetec Corporation. All rights reserved.
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* Written by Hashimoto Kenichi for Genetec Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_IMX_IMXCSPIREG_H_
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#define _ARM_IMX_IMXCSPIREG_H_
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#define CSPI_RXDATA 0x00
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#define CSPI_TXDATA 0x04
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#define CSPI_CONREG 0x08
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#ifdef IMX51
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#define CSPI_CON_CS __BITS(13, 12)
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#define CSPI_CON_DRCTL __BITS( 9, 8)
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#define CSPI_CON_BITCOUNT __BITS(31, 20)
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#else
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#define CSPI_CON_CS __BITS(25, 24)
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#define CSPI_CON_DRCTL __BITS(21, 20)
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#define CSPI_CON_BITCOUNT __BITS(12, 8)
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#endif
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#define CSPI_CON_DIV __BITS(18, 16)
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#define CSPI_CON_SSPOL __BIT(7) /* SPI SS Polarity Select */
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#define CSPI_CON_SSCTL __BIT(6) /* In master mode, this bit
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* selects the output wave form
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* for the SS signal.
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*/
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#define CSPI_CON_PHA __BIT(5) /* PHA */
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#define CSPI_CON_POL __BIT(4) /* POL */
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#define CSPI_CON_SMC __BIT(3) /* SMC */
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#define CSPI_CON_XCH __BIT(2) /* XCH */
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#define CSPI_CON_MODE __BIT(1) /* MODE */
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#define CSPI_CON_ENABLE __BIT(0) /* EN */
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#define CSPI_INTREG 0x0c
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#define CSPI_INTR_ALL_EN 0x000001ff /* All Intarruption Enabled */
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#ifdef IMX51
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#define CSPI_INTR_TC_EN __BIT(7) /* TX Complete */
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#else
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#define CSPI_INTR_TC_EN __BIT(8) /* TX Complete */
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#define CSPI_INTR_BO_EN __BIT(7) /* Bit Counter Overflow */
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#endif
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#define CSPI_INTR_RO_EN __BIT(6) /* RXFIFO Overflow */
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#define CSPI_INTR_RF_EN __BIT(5) /* RXFIFO Full */
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#define CSPI_INTR_RH_EN __BIT(4) /* RXFIFO Half Full */
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#define CSPI_INTR_RR_EN __BIT(3) /* RXFIFO Ready */
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#define CSPI_INTR_TF_EN __BIT(2) /* TXFIFO Full */
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#define CSPI_INTR_TH_EN __BIT(1) /* TXFIFO Half Empty */
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#define CSPI_INTR_TE_EN __BIT(0) /* TXFIFO Empty */
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#define CSPI_DMAREG 0x10
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#define CSPI_STATREG 0x14
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#ifdef IMX51
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#define CSPI_STAT_CLR_TC __BIT(7) /* Clear TC of status register */
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#define CSPI_STAT_CLR CSPI_STAT_CLR_TC
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#else
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#define CSPI_STAT_CLR_TC __BIT(8) /* Clear TC of status register */
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#define CSPI_STAT_CLR_BO __BIT(7) /* Clear BO of status register */
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#define CSPI_STAT_CLR (CSPI_STAT_CLR_TC | CSPI_STAT_CLR_BO)
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#endif
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#define CSPI_STAT_RO __BIT(6) /* RXFIFO Overflow */
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#define CSPI_STAT_RF __BIT(5) /* RXFIFO Full */
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#define CSPI_STAT_RH __BIT(4) /* RXFIFO Half Full */
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#define CSPI_STAT_RR __BIT(3) /* RXFIFO Ready */
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#define CSPI_STAT_TF __BIT(2) /* TXFIFO Full */
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#define CSPI_STAT_TH __BIT(1) /* TXFIFO Half Empty */
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#define CSPI_STAT_TE __BIT(0) /* TXFIFO Empty */
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#define CSPI_PERIODREG 0x18
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#define CSPI_TESTREG 0x1c
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#define SPI_SIZE 0x100
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#endif /* _ARM_IMX_IMXCSPIREG_H_ */
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