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81 lines
3.6 KiB
C
81 lines
3.6 KiB
C
/* $NetBSD: imxecspireg.h,v 1.1 2014/03/22 09:28:08 hkenken Exp $ */
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/*
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* Copyright (c) 2012 Genetec Corporation. All rights reserved.
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* Written by Hashimoto Kenichi for Genetec Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_IMX_IMXECSPIREG_H_
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#define _ARM_IMX_IMXECSPIREG_H_
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#define ECSPI_RXDATA 0x00
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#define ECSPI_TXDATA 0x04
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#define ECSPI_CONREG 0x08
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#define ECSPI_CON_BITCOUNT __BITS(31, 20)
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#define ECSPI_CON_CS __BITS(19,18)
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#define ECSPI_CON_DRCTL __BITS(17,16)
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#define ECSPI_CON_PREDIV __BITS(15,12) /* PRE DIVIDER */
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#define ECSPI_CON_DIV __BITS(11, 8) /* POST DIVIDER */
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#define ECSPI_CON_MODE __BITS( 7, 4) /* MODE */
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#define ECSPI_CON_SMC __BIT(3) /* SMC */
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#define ECSPI_CON_XCH __BIT(2) /* XCH */
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#define ECSPI_CON_HW __BIT(1) /* HW */
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#define ECSPI_CON_ENABLE __BIT(0) /* EN */
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#define ECSPI_CONFIGREG 0x0c
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#define ECSPI_CONFIG_HT_LEN __BITS(28,24) /* HT LENGHT */
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#define ECSPI_CONFIG_SCLK_CTL __BITS(23,20) /* SCLK CTL */
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#define ECSPI_CONFIG_DATA_CTL __BITS(19,16) /* DATA CTL */
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#define ECSPI_CONFIG_SSB_POL __BITS(15,12) /* SSB POL */
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#define ECSPI_CONFIG_SSB_CTL __BITS(11, 8) /* SSB CTL */
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#define ECSPI_CONFIG_SCLK_POL __BITS( 7, 4) /* SCLK POL */
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#define ECSPI_CONFIG_SCLK_PHA __BITS( 3, 0) /* SCLK PHA */
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#define ECSPI_INTREG 0x10
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#define ECSPI_INTR_ALL_EN __BITS( 7, 0) /* All Intarruption Enabled */
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#define ECSPI_INTR_TC_EN __BIT(7) /* TX Complete */
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#define ECSPI_INTR_RO_EN __BIT(6) /* RXFIFO Overflow */
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#define ECSPI_INTR_RF_EN __BIT(5) /* RXFIFO Full */
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#define ECSPI_INTR_RD_EN __BIT(4) /* RXFIFO Data Request */
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#define ECSPI_INTR_RR_EN __BIT(3) /* RXFIFO Ready */
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#define ECSPI_INTR_TF_EN __BIT(2) /* TXFIFO Full */
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#define ECSPI_INTR_TD_EN __BIT(1) /* TXFIFO Data Request */
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#define ECSPI_INTR_TE_EN __BIT(0) /* TXFIFO Empty */
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#define ECSPI_DMAREG 0x14
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#define ECSPI_STATREG 0x18
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#define ECSPI_STAT_CLR_TC __BIT(7) /* Clear Transfer Completed */
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#define ECSPI_STAT_CLR_RO __BIT(6) /* Clear RXFIFO Overflow */
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#define ECSPI_STAT_CLR ECSPI_STAT_CLR_TC
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#define ECSPI_STAT_RF __BIT(5)
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#define ECSPI_STAT_RDR __BIT(4)
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#define ECSPI_STAT_RR __BIT(3)
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#define ECSPI_STAT_TF __BIT(2)
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#define ECSPI_STAT_TDR __BIT(1)
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#define ECSPI_STAT_TE __BIT(0)
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#define ECSPI_PERIODREG 0x1c
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#define ECSPI_TESTREG 0x20
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#define ECSPI_MSGDATA 0x40
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#define ECSPI_SIZE 0x50
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#endif /* _ARM_IMX_IMXECSPIREG_H_ */
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