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67 lines
2.6 KiB
C
67 lines
2.6 KiB
C
/* $NetBSD: imxpwmreg.h,v 1.1 2014/05/06 11:22:53 hkenken Exp $ */
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/*
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* Copyright (c) 2014 Genetec Corporation. All rights reserved.
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* Written by Hashimoto Kenichi for Genetec Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_IMX_IMXPWMREG_H_
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#define _ARM_IMX_IMXPWMREG_H_
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#define PWM_CR 0x00 /* PWM Control Register */
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#define CR_FWM __BITS(27, 26)
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#define CR_STOPEN __BIT(25)
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#define CR_DOZEN __BIT(24)
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#define CR_WAITEN __BIT(23)
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#define CR_DBGEN __BIT(22)
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#define CR_BCTR __BIT(21)
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#define CR_HCTR __BIT(20)
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#define CR_POUTC __BITS(19, 18)
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#define CR_CLKSRC __BITS(17, 16)
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#define CLKSRC_IPG_CLK 1
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#define CLKSRC_IPG_CLK_HIGHFREQ 2
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#define CLKSRC_IPG_CLK_32K 3
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#define CR_PRESCALER __BITS(15, 4)
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#define CR_SWR __BIT(3)
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#define CR_REPEAT __BITS(2, 1)
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#define CR_EN __BIT(0)
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#define PWM_SR 0x04 /* PWM Status Register */
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#define SR_FWE __BIT(6)
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#define SR_CMP __BIT(5)
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#define SR_ROV __BIT(4)
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#define SR_FE __BIT(3)
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#define SR_FIFOAV __BITS(2, 0)
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#define PWM_IR 0x08 /* PWM Interrupt Register */
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#define IR_CIE __BIT(2)
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#define IR_RIE __BIT(1)
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#define IR_FIE __BIT(0)
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#define PWM_SAR 0x0C /* PWM Sample Register */
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#define SAR_SAMPLE __BITS(15, 0)
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#define PWM_PR 0x10 /* PWM Period Register */
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#define PR_PERIOD __BITS(15, 0)
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#define PWM_CNR 0x14 /* PWM Counter Register */
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#define CNR_COUNT __BITS(15, 0)
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#endif /* _ARM_IMX_IMXPWMREG_H_ */
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