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470 lines
17 KiB
C
470 lines
17 KiB
C
/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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Developed by Semihalf
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********************************************************************************
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Marvell BSD License
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File under the following licensing terms.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Marvell nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#ifndef _ARMADAXPREG_H_
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#define _ARMADAXPREG_H_
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#include <arm/marvell/mvsocreg.h>
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#include <evbarm/marvell/marvellvar.h>
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#define ARMADAXP_UNITID_DDR MVSOC_UNITID_DDR
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#define ARMADAXP_UNITID_DEVBUS MVSOC_UNITID_DEVBUS
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#define ARMADAXP_UNITID_MLMB MVSOC_UNITID_MLMB
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#define ARMADAXP_UNITID_PEX MVSOC_UNITID_PEX
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#define ARMADAXP_UNITID_USB 0x5 /* USB registers */
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#define ARMADAXP_UNITID_XORE0 0x6 /* Reserved? */
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#define ARMADAXP_UNITID_GBE0 0x7
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#define ARMADAXP_UNITID_GBE1 0x7
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#define ARMADAXP_UNITID_GBE2 0x3
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#define ARMADAXP_UNITID_GBE3 0x3
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#define ARMADAXP_UNITID_PEX0 MVSOC_UNITID_PEX
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#define ARMADAXP_UNITID_PEX1 0x8
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#define ARMADAXP_UNITID_PEX2 MVSOC_UNITID_PEX
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#define ARMADAXP_UNITID_PEX3 0x8
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#define ARMADAXP_UNITID_CRYPT 0x9
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#define ARMADAXP_UNITID_SATA 0xa
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#define ARMADAXP_UNITID_BM 0xc
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#define ARMADAXP_UNITID_NAND 0xd /* NAND registers */
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#define ARMADAXP_UNITID_SDIO 0xd /* SDIO registers */
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#define ARMADAXP_UNITID_LCD 0xe
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#define ARMADAXP_UNITID_XORE1 0xf
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/* DDR Attributes */
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#define ARMADAXP_ATTR_DDR_CS0 0x0e
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#define ARMADAXP_ATTR_DDR_CS1 0x0d
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#define ARMADAXP_ATTR_DDR_CS2 0x0b
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#define ARMADAXP_ATTR_DDR_CS3 0x07
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/* DEVBUS Attributes */
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#define ARMADAXP_ATTR_DEVBUS_UART 0x01
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#define ARMADAXP_ATTR_DEVBUS_SPI0_CS0 0x1e
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#define ARMADAXP_ATTR_DEVBUS_SPI0_CS1 0x5e
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#define ARMADAXP_ATTR_DEVBUS_SPI0_CS2 0x9e
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#define ARMADAXP_ATTR_DEVBUS_SPI0_CS3 0xde
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#define ARMADAXP_ATTR_DEVBUS_SPI0_CS4 0x1f
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#define ARMADAXP_ATTR_DEVBUS_SPI0_CS5 0x5f
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#define ARMADAXP_ATTR_DEVBUS_SPI0_CS6 0x9f
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#define ARMADAXP_ATTR_DEVBUS_SPI0_CS7 0xdf
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#define ARMADAXP_ATTR_DEVBUS_SPI1_CS0 0x1a
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#define ARMADAXP_ATTR_DEVBUS_SPI1_CS1 0x5a
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#define ARMADAXP_ATTR_DEVBUS_SPI1_CS2 0x9a
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#define ARMADAXP_ATTR_DEVBUS_SPI1_CS3 0xda
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#define ARMADAXP_ATTR_DEVBUS_SPI1_CS4 0x1b
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#define ARMADAXP_ATTR_DEVBUS_SPI1_CS5 0x5b
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#define ARMADAXP_ATTR_DEVBUS_SPI1_CS6 0x9b
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#define ARMADAXP_ATTR_DEVBUS_SPI1_CS7 0xdb
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#define ARMADAXP_ATTR_DEVBUS_DEV_CS0 0x3e
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#define ARMADAXP_ATTR_DEVBUS_DEV_CS1 0x3d
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#define ARMADAXP_ATTR_DEVBUS_DEV_CS2 0x3b
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#define ARMADAXP_ATTR_DEVBUS_DEV_CS3 0x37
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#define ARMADAXP_ATTR_DEVBUS_BOOT_CS 0x2f
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#define ARMADAXP_ATTR_DEVBUS_BOOT_ROM 0x1d
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/* NAND Attributes */
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#define ARMADAXP_ATTR_NAND_RESERVED 0x20
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/* PCIe Attributes */
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/* port 0, 1 has 4 lanes */
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#define ARMADAXP_ATTR_PEXx0_MEM 0xe8
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#define ARMADAXP_ATTR_PEXx0_IO 0xe0
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#define ARMADAXP_ATTR_PEXx1_MEM 0xd8
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#define ARMADAXP_ATTR_PEXx1_IO 0xd0
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#define ARMADAXP_ATTR_PEXx2_MEM 0xb8
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#define ARMADAXP_ATTR_PEXx2_IO 0xb0
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#define ARMADAXP_ATTR_PEXx3_MEM 0x78
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#define ARMADAXP_ATTR_PEXx3_IO 0x70
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/* port 2, 3 has only 1 lane */
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#define ARMADAXP_ATTR_PEX2_MEM 0xf8
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#define ARMADAXP_ATTR_PEX2_IO 0xf0
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#define ARMADAXP_ATTR_PEX3_MEM 0xf8
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#define ARMADAXP_ATTR_PEX3_IO 0xf0
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/* GbE Attributes */
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#define ARMADAXP_ATTR_GBE_RESERVED 0x00
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/* BM Attributes */
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#define ARMADAXP_ATTR_BM_RESERVED 0x00
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/* CRYPT Attributes */
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#define ARMADAXP_ATTR_CRYPT_SWAP_MASK __BITS(1,0)
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#define ARMADAXP_ATTR_CRYPT_SWAP_B (0x0 << 0)
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#define ARMADAXP_ATTR_CRYPT_SWAP_NONE (0x1 << 0)
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#define ARMADAXP_ATTR_CRYPT_SWAP_BW (0x2 << 0)
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#define ARMADAXP_ATTR_CRYPT_SWAP_W (0x3 << 0)
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#define ARMADAXP_ATTR_CRYPT_UNIT_MASK __BITS(3,2)
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#define ARMADAXP_ATTR_CRYPT_UNIT0 (0x1 << 2)
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#define ARMADAXP_ATTR_CRYPT_UNIT1 (0x2 << 2)
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#define ARMADAXP_ATTR_CRYPT0_NOSWAP \
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(ARMADAXP_ATTR_CRYPT_SWAP_NONE|ARMADAXP_ATTR_CRYPT_UNIT0)
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#define ARMADAXP_ATTR_CRYPT0_SWAP_BYTE \
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(ARMADAXP_ATTR_CRYPT_SWAP_B|ARMADAXP_ATTR_CRYPT_UNIT0)
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#define ARMADAXP_ATTR_CRYPT0_SWAP_BYTE_WORD \
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(ARMADAXP_ATTR_CRYPT_SWAP_BW|ARMADAXP_ATTR_CRYPT_UNIT0)
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#define ARMADAXP_ATTR_CRYPT0_SWAP_WORD \
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(ARMADAXP_ATTR_CRYPT_SWAP_W|ARMADAXP_ATTR_CRYPT_UNIT0)
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#define ARMADAXP_ATTR_CRYPT1_NOSWAP \
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(ARMADAXP_ATTR_CRYPT_SWAP_NONE|ARMADAXP_ATTR_CRYPT_UNIT1)
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#define ARMADAXP_ATTR_CRYPT1_SWAP_BYTE \
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(ARMADAXP_ATTR_CRYPT_SWAP_B|ARMADAXP_ATTR_CRYPT_UNIT1)
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#define ARMADAXP_ATTR_CRYPT1_SWAP_BYTE_WORD \
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(ARMADAXP_ATTR_CRYPT_SWAP_BW|ARMADAXP_ATTR_CRYPT_UNIT1)
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#define ARMADAXP_ATTR_CRYPT1_SWAP_WORD \
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(ARMADAXP_ATTR_CRYPT_SWAP_W|ARMADAXP_ATTR_CRYPT_UNIT1)
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#define ARMADAXP_IRQ_ERR_SUMMARY 4
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#define ARMADAXP_IRQ_GBE0_TH_RXTX 8 /* GBE0_TH_RXTX_Int */
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#define ARMADAXP_IRQ_GBE1_TH_RXTX 10 /* GBE1_TH_RXTX_Int */
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#define ARMADAXP_IRQ_GBE2_TH_RXTX 12 /* GBE2_TH_RXTX_Int */
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#define ARMADAXP_IRQ_GBE3_TH_RXTX 14 /* GBE3_TH_RXTX_Int */
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#define ARMADAXP_IRQ_LCD 29
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#define ARMADAXP_IRQ_SPI 30
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#define ARMADAXP_IRQ_TWSI0 31
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#define ARMADAXP_IRQ_TWSI1 32
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#define ARMADAXP_IRQ_IDMA0 33 /* IDMA Channel 0 */
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#define ARMADAXP_IRQ_IDMA1 34 /* IDMA Channel 1 */
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#define ARMADAXP_IRQ_IDMA2 35 /* IDMA Channel 2 */
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#define ARMADAXP_IRQ_IDMA3 36 /* IDMA Channel 3 */
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#define ARMADAXP_IRQ_TIMER0 37
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#define ARMADAXP_IRQ_TIMER1 38
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#define ARMADAXP_IRQ_TIMER2 39
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#define ARMADAXP_IRQ_TIMER3 40
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#define ARMADAXP_IRQ_UART0 41
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#define ARMADAXP_IRQ_UART1 42
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#define ARMADAXP_IRQ_UART2 43
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#define ARMADAXP_IRQ_UART3 44
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#if 0
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#define ARMADAXP_IRQ_USB0 45
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#define ARMADAXP_IRQ_USB1 46
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#define ARMADAXP_IRQ_USB2 47
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#else
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/*
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* According to functional specification (MV-S107021-00B.pdf), interrupt number
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* for USB0_int is 47, in fact this number is 45. Because of that interrupt
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* number definitions are not equivalent to ArmadaXP functional specification
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* (MV-S107021-00B.pdf).
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*/
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#define ARMADAXP_IRQ_USB0 45 /* USB2 */
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#define ARMADAXP_IRQ_USB1 46 /* USB1 */
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#define ARMADAXP_IRQ_USB2 47 /* USB0 */
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#endif
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#define ARMADAXP_IRQ_CESA0 48
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#define ARMADAXP_IRQ_CESA1 49
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#define ARMADAXP_IRQ_RTC 50
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#define ARMADAXP_IRQ_XOR0CH0 51 /* XOR0 Ch0 */
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#define ARMADAXP_IRQ_XOR0CH1 52 /* XOR0 Ch1 */
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#define ARMADAXP_IRQ_BM 53 /* Buffer Management */
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#define ARMADAXP_IRQ_SDIO 54
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#define ARMADAXP_IRQ_SATA0 55
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#define ARMADAXP_IRQ_TDM 56
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#define ARMADAXP_IRQ_SATA1 57
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#define ARMADAXP_IRQ_PEX00 58 /* PCIe Port0.0 INTA/B/C/D */
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#define ARMADAXP_IRQ_PEX01 59 /* PCIe Port0.1 INTA/B/C/D */
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#define ARMADAXP_IRQ_PEX02 60 /* PCIe Port0.2 INTA/B/C/D */
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#define ARMADAXP_IRQ_PEX03 61 /* PCIe Port0.3 INTA/B/C/D */
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#define ARMADAXP_IRQ_PEX10 62 /* PCIe Port1.0 INTA/B/C/D */
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#define ARMADAXP_IRQ_PEX11 63 /* PCIe Port1.1 INTA/B/C/D */
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#define ARMADAXP_IRQ_PEX12 64 /* PCIe Port1.2 INTA/B/C/D */
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#define ARMADAXP_IRQ_PEX13 65 /* PCIe Port1.3 INTA/B/C/D */
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#define ARMADAXP_IRQ_XOR1CH2 94 /* XOR1 Ch2 */
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#define ARMADAXP_IRQ_XOR1CH3 95 /* XOR1 Ch3 */
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#define ARMADAXP_IRQ_PEX2 99 /* PCIe Port2 INTA/B/C/D */
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#define ARMADAXP_IRQ_PEX3 103 /* PCIe Port3 INTA/B/C/D */
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#define ARMADAXP_IRQ_SOURCES 116
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/*
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* IRQ mappings for Error Interrupt Cause(ARMADAXP_MLMB_MPIC_ERR_CAUSE)
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*/
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#define ARMADAXP_IRQ_ERROR_BASE 120
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#define ARMADAXP_IRQ_ERROR_SOURCES 32
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#define ARMADAXP_IRQ_ERROR(x) (120 + (x))
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#define ARMADAXP_IRQ_ERROR_BIT(irq) (1 << irq)
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#define ARMADAXP_IRQ_CESA0_ERR ARMADAXP_IRQ_ERROR(0)
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#define ARMADAXP_IRQ_DEVBUS_ERR ARMADAXP_IRQ_ERROR(1)
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#define ARMADAXP_IRQ_IDMA_ERR ARMADAXP_IRQ_ERROR(2)
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#define ARMADAXP_IRQ_XOR1_ERR ARMADAXP_IRQ_ERROR(3)
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#define ARMADAXP_IRQ_PEX0_ERR ARMADAXP_IRQ_ERROR(4)
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#define ARMADAXP_IRQ_PEX1_ERR ARMADAXP_IRQ_ERROR(5)
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#define ARMADAXP_IRQ_GBE_ERR ARMADAXP_IRQ_ERROR(6)
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#define ARMADAXP_IRQ_CESA1_ERR ARMADAXP_IRQ_ERROR(7)
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#define ARMADAXP_IRQ_USB_ERR ARMADAXP_IRQ_ERROR(8)
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#define ARMADAXP_IRQ_DRAM_ERR ARMADAXP_IRQ_ERROR(9)
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#define ARMADAXP_IRQ_XOR0_ERR ARMADAXP_IRQ_ERROR(10)
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#define ARMADAXP_IRQ_BM_ERR ARMADAXP_IRQ_ERROR(12)
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#define ARMADAXP_IRQ_CIB_ERR ARMADAXP_IRQ_ERROR(13)
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#define ARMADAXP_IRQ_PEX2_ERR ARMADAXP_IRQ_ERROR(15)
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#define ARMADAXP_IRQ_PEX3_ERR ARMADAXP_IRQ_ERROR(16)
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#define ARMADAXP_IRQ_SATA0_ERR ARMADAXP_IRQ_ERROR(17)
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#define ARMADAXP_IRQ_SATA1_ERR ARMADAXP_IRQ_ERROR(18)
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#define ARMADAXP_IRQ_TDM_ERR ARMADAXP_IRQ_ERROR(20)
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#define ARMADAXP_IRQ_NAND_ERR ARMADAXP_IRQ_ERROR(21)
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#define ARMADAXP_MLMB_NWINDOW 20
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#define ARMADAXP_MLMB_NREMAP 8
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/*
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* Physical address of integrated peripherals
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*/
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#undef UNITID2PHYS
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#define UNITID2PHYS(uid) ((ARMADAXP_UNITID_ ## uid) << 16)
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/*
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* Real-Time Clock Unit Registers
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*/
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#define ARMADAXP_RTC_BASE (MVSOC_DEVBUS_BASE + 0x0300)
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/*
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* SPI Interface Registers
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*/
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#define ARMADAXP_SPI_BASE (MVSOC_DEVBUS_BASE + 0x0600)
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/*
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* TWSI Interface Registers
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*/
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#define ARMADAXP_TWSI1_BASE (MVSOC_DEVBUS_BASE + 0x1100)
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/*
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* UART Interface Registers
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*/ /* NS16550 compatible */
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#define ARMADAXP_COM2_BASE (MVSOC_DEVBUS_BASE + 0x2200)
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#define ARMADAXP_COM3_BASE (MVSOC_DEVBUS_BASE + 0x2300)
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/*
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* General Purpose Input/Output Port Registers
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*/
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#define ARMADAXP_GPIO0_BASE (MVSOC_DEVBUS_BASE + 0x8100)
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#define ARMADAXP_GPIO1_BASE (MVSOC_DEVBUS_BASE + 0x8120)
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#define ARMADAXP_GPIO2_BASE (MVSOC_DEVBUS_BASE + 0x8140)
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/*
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* Power Management Unit Registers
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*/ /* NS16550 compatible */
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#define ARMADAXP_PMU_BASE (MVSOC_DEVBUS_BASE + 0xc000)
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/*
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* Miscellanseous Register
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*/
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#define ARMADAXP_MISC_BASE (MVSOC_DEVBUS_BASE + 0x8200)
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#define ARMADAXP_MISC_PMCGC 0x20 /* PM Clock Gating Control */
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#define ARMADAXP_MISC_SAR_LO 0x30 /* Sample At Reset Low */
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#define ARMADAXP_MISC_SAR_HI 0x34 /* Sample At Reset High */
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#define ARMADAXP_MISC_RSTOUTNMASKR 0x60 /* RSTOUTn Mask Register */
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#define ARMADAXP_MISC_RSTOUTNMASKR_GLOBALSOFTRSTOUTEN (1 << 0)
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#define ARMADAXP_MISC_SSRR 0x64 /* System Soft Reset Register */
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#define ARMADAXP_MISC_SSRR_GLOBALSOFTRST (1 << 0)
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/* Multiprocessor Interrupt Controller Registers */
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#define ARMADAXP_MLMB_MPIC_BASE 0x20a00
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#define ARMADAXP_MLMB_MPIC_CPU_BASE 0x21800
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#define ARMADAXP_MLMB_MPIC_CTRL 0x0
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#define ARMADAXP_MLMB_MPIC_SOFT_INT 0x4
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#define ARMADAXP_MLMB_MPIC_ERR_CAUSE 0x20
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#define ARMADAXP_MLMB_MPIC_ISE 0x30
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#define ARMADAXP_MLMB_MPIC_ICE 0x34
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#define ARMADAXP_MLMB_MPIC_ISCR_BASE 0x100
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#define ARMADAXP_MLMB_MPIC_DOORBELL 0x78
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#define ARMADAXP_MLMB_MPIC_DOORBELL_MASK 0x7c
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#define ARMADAXP_MLMB_MPIC_CTP 0xb0
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#define ARMADAXP_MLMB_MPIC_IIACK 0xb4
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#define ARMADAXP_MLMB_MPIC_ISM 0xb8
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#define ARMADAXP_MLMB_MPIC_ICM 0xbc
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#define ARMADAXP_MLMB_MPIC_ERR_MASK 0xc0
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/* Multiprocessor Interrupt Controller Shifts */
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#define MPIC_CTP_SHIFT 28 /* Global priority level field */
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#define MPIC_ISCR_SHIFT 24 /* IRQ source priority level field */
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/* Cache Main Control */
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#define ARMADAXP_L2_BASE 0x8000
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#define ARMADAXP_L2_CTRL 0x100
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#define ARMADAXP_L2_AUX_CTRL 0x104
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#define ARMADAXP_L2_CNTR_CTRL 0x200
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#define ARMADAXP_L2_CNTR_CONF(x) (0x204 + (x) * 0xc)
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#define ARMADAXP_L2_INT_CAUSE 0x220
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#define ARMADAXP_L2_CFU 0x228
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#define ARMADAXP_L2_SYNC 0x700
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#define ARMADAXP_L2_STATUS 0x704
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/* Cache maintance operations */
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#define ARMADAXP_L2_RANGE_BASE 0x720
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#define ARMADAXP_L2_INV_PHYS 0x770
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#define ARMADAXP_L2_INV_RANGE 0x774
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#define ARMADAXP_L2_INV_IDXWAY 0x778
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#define ARMADAXP_L2_INV_WAY 0x77c
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#define ARMADAXP_L2_BLOCK 0x78c
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#define ARMADAXP_L2_WB_PHYS 0x7b0
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#define ARMADAXP_L2_WB_RANGE 0x7b4
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#define ARMADAXP_L2_WB_IDXWAY 0x7b8
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#define ARMADAXP_L2_WB_WAY 0x7bc
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#define ARMADAXP_L2_WBINV_PHYS 0x7f0
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#define ARMADAXP_L2_WBINV_RANGE 0x7f4
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#define ARMADAXP_L2_WBINV_IDXWAY 0x7f8
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#define ARMADAXP_L2_WBINV_WAY 0x7fc
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/* Cache line size */
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#define ARMADAXP_L2_SIZE (256 * 1024) /* bytes */
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#define ARMADAXP_L2_LINE_SIZE 32
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#define ARMADAXP_L2_ALIGN (ARMADAXP_L2_LINE_SIZE - 1)
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#define ARMADAXP_L2_WAYS 4
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#define ARMADAXP_L2_WAY_SIZE (ARMADAXP_L2_SIZE / ARMADAXP_L2_WAYS)
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#define ARMADAXP_L2_SETS \
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(ARMADAXP_L2_WAY_SIZE / ARMADAXP_L2_LINE_SIZE)
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/* ARMADAXP_L2_CTRL */
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#define L2_CTRL_ENABLE (1 << 0)
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/* ARMADAXP_L2_AUX_CTRL */
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#define L2_AUX_WBWT_MODE_MASK __BITS(1,0)
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#define L2_AUX_WBWT_MODE_BY_ATTR (0 << 0)
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#define L2_AUX_WBWT_MODE_WB (1 << 0)
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#define L2_AUX_WBWT_MODE_WT (2 << 0)
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#define L2_AUX_FLUSH_ON_POWERDOWN __BIT(3)
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#define L2_AUX_ECC_ENABLE __BIT(20)
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#define L2_AUX_PARITY_ENABLE __BIT(21)
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#define L2_AUX_INVAL_UCE __BIT(22)
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#define L2_AUX_FORCE_WA_MASK __BITS(24,23)
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#define L2_AUX_FORCE_WA_BY_ATTR (0 << 23)
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#define L2_AUX_FORCE_WA_DISABLE (1 << 23)
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#define L2_AUX_FORCE_WA_ENABLE (2 << 23)
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#define L2_AUX_FORCE_WA_ENABLE_DT (3 << 23)
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#define L2_AUX_REP_STRAT_MASK (3 << 27)
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#define L2_AUX_REP_STRAT_LFSR (1 << 27)
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#define L2_AUX_REP_STRAT_PLRU (2 << 27)
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#define L2_AUX_REP_STRAT_SEMIPLRU (3 << 27)
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#define L2_AUX_L2_SIZE_MASK (0x03 << 10)
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#define L2_AUX_L2_SIZE_256K (0x00 << 10)
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#define L2_AUX_L2_ASSOC_MASK (0x0f << 13)
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#define L2_AUX_L2_ASSOC_4WAY (0x03 << 13)
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#define L2_AUX_L2_WAY_MASK (0x07 << 17)
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#define L2_AUX_L2_WAY_16K (0x02 << 17)
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#define L2_AUX_L2_WAY_32K (0x03 << 17)
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#define L2_AUX_L2_WAY_64K (0x04 << 17)
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#define L2_AUX_L2_WAY_128K (0x05 << 17)
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#define L2_AUX_L2_WAY_256K (0x06 << 17)
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#define L2_AUX_L2_WAY_512K (0x07 << 17)
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#define L2_ALL_WAYS 0xffffffff
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/*
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* PCI-Express Interface Registers
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*/
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#define ARMADAXP_PEX01_BASE (MVSOC_PEX_BASE + 0x4000)
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#define ARMADAXP_PEX02_BASE (MVSOC_PEX_BASE + 0x8000)
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#define ARMADAXP_PEX03_BASE (MVSOC_PEX_BASE + 0xc000)
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#define ARMADAXP_PEX10_BASE (UNITID2PHYS(PEX1))
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#define ARMADAXP_PEX11_BASE (ARMADAXP_PEX10_BASE + 0x4000)
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#define ARMADAXP_PEX12_BASE (ARMADAXP_PEX10_BASE + 0x8000)
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#define ARMADAXP_PEX13_BASE (ARMADAXP_PEX10_BASE + 0xc000)
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#define ARMADAXP_PEX2_BASE (UNITID2PHYS(PEX2) + 0x2000)
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#define ARMADAXP_PEX3_BASE (UNITID2PHYS(PEX3) + 0x2000)
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/*
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* USB 2.0 Interface Registers
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*/
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#define ARMADAXP_USB_BASE (UNITID2PHYS(USB)) /* 0x50000 */
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#define ARMADAXP_USB0_BASE (ARMADAXP_USB_BASE + 0x0000)
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#define ARMADAXP_USB1_BASE (ARMADAXP_USB_BASE + 0x1000)
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#define ARMADAXP_USB2_BASE (ARMADAXP_USB_BASE + 0x2000)
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/*
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* XOR Engine Registers
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*/
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#define ARMADAXP_XORE0_BASE (UNITID2PHYS(XORE0)) /* 0x60000 */
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#define ARMADAXP_XORE1_BASE (UNITID2PHYS(XORE1)) /* 0xf0000 */
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/*
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* Gigabit Ethernet Registers
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*/
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#define ARMADAXP_GBE0_BASE (UNITID2PHYS(GBE0)) /* 0x70000 */
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#define ARMADAXP_GBE1_BASE (ARMADAXP_GBE0_BASE + 0x4000)
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#define ARMADAXP_GBE2_BASE (UNITID2PHYS(GBE2)) /* 0x30000 */
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#define ARMADAXP_GBE3_BASE (ARMADAXP_GBE2_BASE + 0x4000)
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/*
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* Precise Time Protocol (PTP) Registers
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*/
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#define ARMADAXP_PTP_BASE (UNITID2PHYS(GBE0)) /* 0x7c000 */
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/*
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* Cryptographic Engine and Security Accelerator Registers
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*/
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#define ARMADAXP_CESA0_BASE (UNITID2PHYS(CRYPT) + 0xd000) /* 0x9d000 */
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#define ARMADAXP_CESA1_BASE (UNITID2PHYS(CRYPT) + 0xf000) /* 0x9f000 */
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#define ARMADAXP_XPSEC0_BASE (UNITID2PHYS(CRYPT) + 0x0000) /* 0x90000 */
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#define ARMADAXP_XPSEC1_BASE (UNITID2PHYS(CRYPT) + 0x2000) /* 0x92000 */
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/*
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* Serial-ATA Host Controller (SATAHC) Registers
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*/
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#define ARMADAXP_SATAHC_BASE (UNITID2PHYS(SATA)) /* 0xa0000 */
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/*
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* Buffer Management Controller Registers
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*/
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#define ARMADAXP_BMC_BASE (UNITID2PHYS(BM)) /* 0xc0000 */
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/*
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* NAND Flash Controller Version 2.0 Registers
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*/
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#define ARMADAXP_NAND_BASE (UINTID2PHYS(NAND))
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/*
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* PnC Unit Registers
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*/
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#define ARMADAXP_PNC_BASE (UNITID2PHYS(PNC)) /* 0xc8000 */
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/*
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* SDIO Registers
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*/
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#define ARMADAXP_SDIO_BASE (UNITID2PHYS(SDIO) + 0x4000) /* 0xd4000 */
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/*
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* Liquid Crystal Display Registers
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*/
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#define ARMADAXP_LCD_BASE (UNITID2PHYS(LCD)) /* 0xe0000 */
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#endif /* _ARMADAXPREG_H_ */
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