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472 lines
13 KiB
C
472 lines
13 KiB
C
/* $NetBSD: mvsocgpp.c,v 1.6 2014/01/28 13:17:19 martin Exp $ */
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/*
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* Copyright (c) 2008, 2010 KIYOHARA Takashi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: mvsocgpp.c,v 1.6 2014/01/28 13:17:19 martin Exp $");
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#include "gpio.h"
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#define _INTR_PRIVATE
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <sys/errno.h>
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#include <sys/evcnt.h>
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#include <sys/gpio.h>
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#include <sys/kmem.h>
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#include <machine/intr.h>
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#include <arm/marvell/mvsocreg.h>
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#include <arm/marvell/mvsocvar.h>
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#include <arm/marvell/mvsocgppreg.h>
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#include <arm/marvell/mvsocgppvar.h>
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#include <arm/pic/picvar.h>
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#include <dev/marvell/marvellvar.h>
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#if NGPIO > 0
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#include <sys/gpio.h>
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#include <dev/gpio/gpiovar.h>
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#endif
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#define MVSOCGPP_DUMPREG
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#define MVSOCGPP_READ(sc, reg) \
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bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))
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#define MVSOCGPP_WRITE(sc, reg, val) \
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bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
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struct mvsocgpp_softc {
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device_t sc_dev;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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struct mvsocgpp_pic {
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struct pic_softc gpio_pic;
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int group;
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int shift;
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uint32_t edge;
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uint32_t level;
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} *sc_pic;
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#if NGPIO > 0
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struct gpio_chipset_tag sc_gpio_chipset;
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gpio_pin_t *sc_pins;
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#endif
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};
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static int mvsocgpp_match(device_t, struct cfdata *, void *);
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static void mvsocgpp_attach(device_t, device_t, void *);
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#ifdef MVSOCGPP_DUMPREG
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static void mvsocgpp_dump_reg(struct mvsocgpp_softc *);
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#endif
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static void gpio_pic_unblock_irqs(struct pic_softc *, size_t, uint32_t);
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static void gpio_pic_block_irqs(struct pic_softc *, size_t, uint32_t);
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static int gpio_pic_find_pending_irqs(struct pic_softc *);
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static void gpio_pic_establish_irq(struct pic_softc *, struct intrsource *);
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static struct pic_ops gpio_pic_ops = {
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.pic_unblock_irqs = gpio_pic_unblock_irqs,
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.pic_block_irqs = gpio_pic_block_irqs,
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.pic_find_pending_irqs = gpio_pic_find_pending_irqs,
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.pic_establish_irq = gpio_pic_establish_irq,
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};
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static struct mvsocgpp_softc *mvsocgpp_softc; /* One unit per One SoC */
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int gpp_irqbase = 0;
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int gpp_npins = 0;
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CFATTACH_DECL_NEW(mvsocgpp, sizeof(struct mvsocgpp_softc),
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mvsocgpp_match, mvsocgpp_attach, NULL, NULL);
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/* ARGSUSED */
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static int
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mvsocgpp_match(device_t parent, struct cfdata *match, void *aux)
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{
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struct marvell_attach_args *mva = aux;
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if (strcmp(mva->mva_name, match->cf_name) != 0)
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return 0;
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if (mva->mva_offset == MVA_OFFSET_DEFAULT ||
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mva->mva_irq == MVA_IRQ_DEFAULT)
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return 0;
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mva->mva_size = MVSOC_GPP_SIZE;
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return 1;
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}
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/* ARGSUSED */
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static void
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mvsocgpp_attach(device_t parent, device_t self, void *aux)
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{
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struct mvsocgpp_softc *sc = device_private(self);
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struct marvell_attach_args *mva = aux;
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struct pic_softc *gpio_pic;
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#if NGPIO > 0
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struct gpiobus_attach_args gba;
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gpio_pin_t *pins;
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uint32_t mask, dir, valin, valout, polarity, blink;
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#endif
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int i, j;
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dir = valin = valout = polarity = blink = 0;
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aprint_normal(": Marvell SoC General Purpose I/O Port Interface\n");
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aprint_naive("\n");
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sc->sc_dev = self;
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sc->sc_iot = mva->mva_iot;
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/* Map I/O registers for oriongpp */
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if (bus_space_subregion(mva->mva_iot, mva->mva_ioh,
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mva->mva_offset, mva->mva_size, &sc->sc_ioh)) {
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aprint_error_dev(self, "can't map registers\n");
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return;
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}
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if (gpp_npins > 0)
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aprint_normal_dev(self, "%d gpio pins\n", gpp_npins);
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else {
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aprint_error_dev(self, "gpp_npins not initialized\n");
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return;
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}
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mvsocgpp_softc = sc;
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for (i = 0; i < gpp_npins; i += 32)
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MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIC(i), 0);
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sc->sc_pic =
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kmem_zalloc(sizeof(struct mvsocgpp_pic) * howmany(gpp_npins, 8),
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KM_SLEEP);
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for (i = 0, j = 0; i < gpp_npins; i += 8, j++) {
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gpio_pic = &(sc->sc_pic + j)->gpio_pic;
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gpio_pic->pic_ops = &gpio_pic_ops;
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snprintf(gpio_pic->pic_name, sizeof(gpio_pic->pic_name),
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"%s[%d:%d]", device_xname(self), i + 7, i);
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gpio_pic->pic_maxsources =
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(gpp_npins - i) > 8 ? 8 : gpp_npins - i;
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pic_add(gpio_pic, gpp_irqbase + i);
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aprint_normal_dev(self, "interrupts %d..%d",
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gpp_irqbase + i, gpp_irqbase + i + 7);
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intr_establish(mva->mva_irq + j,
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IPL_HIGH, IST_LEVEL_HIGH, pic_handle_intr, gpio_pic);
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aprint_normal(", intr %d\n", mva->mva_irq + j);
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(sc->sc_pic + j)->group = j;
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(sc->sc_pic + j)->shift = (j & 3) * 8;
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}
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#ifdef MVSOCGPP_DUMPREG
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mvsocgpp_dump_reg(sc);
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#endif
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#if NGPIO > 0
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sc->sc_pins = kmem_zalloc(sizeof(gpio_pin_t) * gpp_npins, KM_SLEEP);
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for (i = 0, mask = 1; i < gpp_npins; i++, mask <<= 1) {
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if ((i & (32 - 1)) == 0) {
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mask = 1;
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dir = MVSOCGPP_READ(sc, MVSOCGPP_GPIODOEC(i));
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valin = MVSOCGPP_READ(sc, MVSOCGPP_GPIODI(i));
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valout = MVSOCGPP_READ(sc, MVSOCGPP_GPIODO(i));
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polarity = MVSOCGPP_READ(sc, MVSOCGPP_GPIODIP(i));
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blink = MVSOCGPP_READ(sc, MVSOCGPP_GPIOBE(i));
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}
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pins = &sc->sc_pins[i];
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pins->pin_num = i;
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pins->pin_caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |
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GPIO_PIN_INVIN | GPIO_PIN_PULSATE);
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if (dir & mask) {
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pins->pin_flags = GPIO_PIN_INPUT;
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pins->pin_state =
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(valin & mask) ? GPIO_PIN_HIGH : GPIO_PIN_LOW;
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} else {
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pins->pin_flags = GPIO_PIN_OUTPUT;
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pins->pin_state =
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(valout & mask) ? GPIO_PIN_HIGH : GPIO_PIN_LOW;
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}
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if (polarity & mask) {
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pins->pin_flags |= GPIO_PIN_INVIN;
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}
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if (blink & mask) {
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pins->pin_flags |= GPIO_PIN_PULSATE;
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}
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}
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sc->sc_gpio_chipset.gp_cookie = sc;
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sc->sc_gpio_chipset.gp_pin_read = mvsocgpp_pin_read;
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sc->sc_gpio_chipset.gp_pin_write = mvsocgpp_pin_write;
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sc->sc_gpio_chipset.gp_pin_ctl = mvsocgpp_pin_ctl;
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gba.gba_gc = &sc->sc_gpio_chipset;
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gba.gba_pins = sc->sc_pins;
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gba.gba_npins = gpp_npins;
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config_found_ia(self, "gpiobus", &gba, gpiobus_print);
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#endif
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}
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/*
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* arch/arm/pic functions.
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*/
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static void
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gpio_pic_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask)
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{
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struct mvsocgpp_softc *sc = mvsocgpp_softc;
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struct mvsocgpp_pic *mvsocgpp_pic = (struct mvsocgpp_pic *)pic;
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uint32_t mask;
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int pin = mvsocgpp_pic->group << 3;
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irq_mask = irq_mask << mvsocgpp_pic->shift;
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MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIC(pin),
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MVSOCGPP_READ(sc, MVSOCGPP_GPIOIC(pin)) & ~irq_mask);
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if (irq_mask & mvsocgpp_pic->edge) {
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mask = MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(pin));
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mask |= (irq_mask & mvsocgpp_pic->edge);
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MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIM(pin), mask);
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}
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if (irq_mask & mvsocgpp_pic->level) {
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mask = MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(pin));
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mask |= (irq_mask & mvsocgpp_pic->level);
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MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOILM(pin), mask);
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}
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}
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/* ARGSUSED */
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static void
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gpio_pic_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask)
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{
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struct mvsocgpp_softc *sc = mvsocgpp_softc;
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struct mvsocgpp_pic *mvsocgpp_pic = (struct mvsocgpp_pic *)pic;
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int pin = mvsocgpp_pic->group << 3;
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irq_mask = irq_mask << mvsocgpp_pic->shift;
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MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIM(pin),
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MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(pin)) & ~irq_mask);
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MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOILM(pin),
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MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(pin)) & ~irq_mask);
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}
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static int
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gpio_pic_find_pending_irqs(struct pic_softc *pic)
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{
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struct mvsocgpp_softc *sc = mvsocgpp_softc;
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struct mvsocgpp_pic *mvsocgpp_pic = (struct mvsocgpp_pic *)pic;
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uint32_t pending;
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int pin = mvsocgpp_pic->group << 3;
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pending = MVSOCGPP_READ(sc, MVSOCGPP_GPIOIC(pin));
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pending &= (0xff << mvsocgpp_pic->shift);
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pending &= (MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(pin)) |
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MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(pin)));
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pending = pending >> mvsocgpp_pic->shift;
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if (pending == 0)
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return 0;
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return pic_mark_pending_sources(pic, 0, pending);
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}
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static void
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gpio_pic_establish_irq(struct pic_softc *pic, struct intrsource *is)
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{
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struct mvsocgpp_softc *sc = mvsocgpp_softc;
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struct mvsocgpp_pic *mvsocgpp_pic = (struct mvsocgpp_pic *)pic;
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uint32_t im, ilm, mask;
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int type, pin;
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type = is->is_type;
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pin = pic->pic_irqbase + is->is_irq - gpp_irqbase;
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mask = MVSOCGPP_GPIOPIN(pin);
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switch (type) {
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case IST_LEVEL_LOW:
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case IST_EDGE_FALLING:
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mvsocgpp_pin_ctl(NULL, pin, GPIO_PIN_INPUT | GPIO_PIN_INVIN);
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break;
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case IST_LEVEL_HIGH:
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case IST_EDGE_RISING:
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mvsocgpp_pin_ctl(NULL, pin, GPIO_PIN_INPUT);
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break;
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default:
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panic("unknwon interrupt type %d for pin %d.\n", type, pin);
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}
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im = MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(pin));
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ilm = MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(pin));
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switch (type) {
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case IST_EDGE_FALLING:
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case IST_EDGE_RISING:
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im |= mask;
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ilm &= ~mask;
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mvsocgpp_pic->edge |= mask;
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mvsocgpp_pic->level &= ~mask;
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break;
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case IST_LEVEL_LOW:
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case IST_LEVEL_HIGH:
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im &= ~mask;
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ilm |= mask;
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mvsocgpp_pic->edge &= ~mask;
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mvsocgpp_pic->level |= mask;
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break;
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}
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MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIM(pin), im);
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MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOILM(pin), ilm);
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}
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/*
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* gpio(4) functions, and can call you.
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*/
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/* ARGSUSED */
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int
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mvsocgpp_pin_read(void *arg, int pin)
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{
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struct mvsocgpp_softc *sc = mvsocgpp_softc;
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uint32_t val;
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KASSERT(sc != NULL);
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val = MVSOCGPP_READ(sc, MVSOCGPP_GPIODI(pin));
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return (val & MVSOCGPP_GPIOPIN(pin)) != 0;
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}
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/* ARGSUSED */
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void
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mvsocgpp_pin_write(void *arg, int pin, int value)
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{
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struct mvsocgpp_softc *sc = mvsocgpp_softc;
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uint32_t old, new, mask = MVSOCGPP_GPIOPIN(pin);
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KASSERT(sc != NULL);
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old = MVSOCGPP_READ(sc, MVSOCGPP_GPIODO(pin));
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if (value)
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new = old | mask;
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else
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new = old & ~mask;
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if (new != old)
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MVSOCGPP_WRITE(sc, MVSOCGPP_GPIODO(pin), new);
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}
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/* ARGSUSED */
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void
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mvsocgpp_pin_ctl(void *arg, int pin, int flags)
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{
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struct mvsocgpp_softc *sc = mvsocgpp_softc;
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uint32_t old, new, mask = MVSOCGPP_GPIOPIN(pin);
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KASSERT(sc != NULL);
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old = MVSOCGPP_READ(sc, MVSOCGPP_GPIODOEC(pin));
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switch (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
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case GPIO_PIN_INPUT:
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new = old | mask;
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break;
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case GPIO_PIN_OUTPUT:
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new = old & ~mask;
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break;
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default:
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return;
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}
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if (new != old)
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MVSOCGPP_WRITE(sc, MVSOCGPP_GPIODOEC(pin), new);
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/* Blink every 2^24 TCLK */
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old = MVSOCGPP_READ(sc, MVSOCGPP_GPIOBE(pin));
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if (flags & GPIO_PIN_PULSATE)
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new = old | mask;
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else
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new = old & ~mask;
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if (new != old)
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MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOBE(pin), new);
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old = MVSOCGPP_READ(sc, MVSOCGPP_GPIODIP(pin));
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if (flags & GPIO_PIN_INVIN)
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new = old | mask;
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else
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new = old & ~mask;
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if (new != old)
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MVSOCGPP_WRITE(sc, MVSOCGPP_GPIODIP(pin), new);
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}
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#ifdef MVSOCGPP_DUMPREG
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static void
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mvsocgpp_dump_reg(struct mvsocgpp_softc *sc)
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{
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aprint_normal_dev(sc->sc_dev, " Data Out: \t0x%08x\n",
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MVSOCGPP_READ(sc, MVSOCGPP_GPIODO(0)));
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aprint_normal_dev(sc->sc_dev, " Data Out Enable Control: \t0x%08x\n",
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MVSOCGPP_READ(sc, MVSOCGPP_GPIODOEC(0)));
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aprint_normal_dev(sc->sc_dev, " Data Blink Enable: \t0x%08x\n",
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MVSOCGPP_READ(sc, MVSOCGPP_GPIOBE(0)));
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aprint_normal_dev(sc->sc_dev, " Data In Polarity: \t0x%08x\n",
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MVSOCGPP_READ(sc, MVSOCGPP_GPIODIP(0)));
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aprint_normal_dev(sc->sc_dev, " Data In: \t0x%08x\n",
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MVSOCGPP_READ(sc, MVSOCGPP_GPIODI(0)));
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aprint_normal_dev(sc->sc_dev, " Interrupt Cause: \t0x%08x\n",
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MVSOCGPP_READ(sc, MVSOCGPP_GPIOIC(0)));
|
|
aprint_normal_dev(sc->sc_dev, " Interrupt Mask: \t0x%08x\n",
|
|
MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(0)));
|
|
aprint_normal_dev(sc->sc_dev, " Interrupt Level Mask: \t0x%08x\n",
|
|
MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(0)));
|
|
|
|
if (gpp_npins <= 32)
|
|
return;
|
|
|
|
aprint_normal_dev(sc->sc_dev, " High Data Out: \t0x%08x\n",
|
|
MVSOCGPP_READ(sc, MVSOCGPP_GPIODO(32)));
|
|
aprint_normal_dev(sc->sc_dev, " High Data Out Enable Ctrl:\t0x%08x\n",
|
|
MVSOCGPP_READ(sc, MVSOCGPP_GPIODOEC(32)));
|
|
aprint_normal_dev(sc->sc_dev, " High Blink Enable: \t0x%08x\n",
|
|
MVSOCGPP_READ(sc, MVSOCGPP_GPIOBE(32)));
|
|
aprint_normal_dev(sc->sc_dev, " High Data In Polarity: \t0x%08x\n",
|
|
MVSOCGPP_READ(sc, MVSOCGPP_GPIODIP(32)));
|
|
aprint_normal_dev(sc->sc_dev, " High Data In: \t0x%08x\n",
|
|
MVSOCGPP_READ(sc, MVSOCGPP_GPIODI(32)));
|
|
aprint_normal_dev(sc->sc_dev, " High Interrupt Cause: \t0x%08x\n",
|
|
MVSOCGPP_READ(sc, MVSOCGPP_GPIOIC(32)));
|
|
aprint_normal_dev(sc->sc_dev, " High Interrupt Mask: \t0x%08x\n",
|
|
MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(32)));
|
|
aprint_normal_dev(sc->sc_dev, " High Interrupt Level Mask:\t0x%08x\n",
|
|
MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(32)));
|
|
}
|
|
#endif
|