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68 lines
2.5 KiB
C
68 lines
2.5 KiB
C
/* $NetBSD: mvsocgppreg.h,v 1.1 2010/10/03 05:49:24 kiyohara Exp $ */
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/*
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* Copyright (c) 2008 KIYOHARA Takashi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MVSOCGPPREG_H_
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#define _MVSOCGPPREG_H_
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#define MVSOC_GPP_SIZE 0x100
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/*
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* General Purpose Port Registers
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*/
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/* GPIO Register Map */
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/* GPIO Data Out */
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#define MVSOCGPP_GPIODO(p) ((((p) & 0x20) << 1) + 0x00)
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/* GPIO Data Out Enable Control */
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#define MVSOCGPP_GPIODOEC(p) ((((p) & 0x20) << 1) + 0x04)
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/* GPIO Blink Enable Control */
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#define MVSOCGPP_GPIOBE(p) ((((p) & 0x20) << 1) + 0x08)
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/* GPIO Data In Polarity */
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#define MVSOCGPP_GPIODIP(p) ((((p) & 0x20) << 1) + 0x0c)
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/* GPIO Data In */
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#define MVSOCGPP_GPIODI(p) ((((p) & 0x20) << 1) + 0x10)
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/* GPIO Interrupt Cause */
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#define MVSOCGPP_GPIOIC(p) ((((p) & 0x20) << 1) + 0x14)
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/* GPIO Interrupt Mask */
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#define MVSOCGPP_GPIOIM(p) ((((p) & 0x20) << 1) + 0x18)
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/* GPIO Interrupt Level Mask */
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#define MVSOCGPP_GPIOILM(p) ((((p) & 0x20) << 1) + 0x1c)
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#define MVSOCGPP_GPIOPIN(pin) (1 << ((pin) & 0x1f))
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/* Out Enable */
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#define MVSOCGPP_GPIODOE_OUT 0
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#define MVSOCGPP_GPIODOE_IN 1
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/* Polarity */
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#define MVSOCGPP_GPIODIP_INVERT 1
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/* Interrupt Mask */
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#define MVSOCGPP_GPIOIM_EDGE 0
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#define MVSOCGPP_GPIOIM_LEVEL 1
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#endif /* _ORIONPCIREG_H_ */
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