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90 lines
3.2 KiB
C
90 lines
3.2 KiB
C
/* $NetBSD: dicreg.h,v 1.1 2011/03/11 03:26:37 bsh Exp $ */
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/*
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* Copyright (c) 2010, 2011 Genetec Corporation. All rights reserved.
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* Written by Hiroyuki Bessho for Genetec Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_MPCORE_DICREG_H
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#define _ARM_MPCORE_DICREG_H
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#include <sys/cdefs.h>
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/*
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* CPU Interrupt Interface Registers (per core)
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*/
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#define CII_CONTROL 0x00
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#define CII_CONTROL_ENABLE __BIT(0)
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#define CII_PRIMASK 0x04
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#define CII_PRIMASK_SHIFT 4
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#define CII_PRIMASK_MASK __BITS(CII_PRIMASK_SHIFT, 7)
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#define CII_PRIMASK_MASKALL (0 << CII_PRIMASK_SHIFT)
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#define CII_PRIMASK_MASKNONE (0x0f << CII_PRIMASK_SHIFT)
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/* NOTE: interrupt level 15 is always masked. */
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#define CII_BINPOINT 0x08
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#define CII_INTACK 0x0c
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#define CII_INTACK_CPUSRC_SHIFT 10
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#define CII_INTACK_CPUSRC_MASK __BITS(CII_INTACK_CPUSRC_SHIFT, 12)
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#define CII_INTACK_INTID_SHIFT 0
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#define CII_INTACK_INTID_MASK __BITS(CII_INTACK_INTID_SHIFT, 9)
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#define CII_EOI 0x10
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#define CII_RUNPRI 0x14 /* Running Priority */
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#define CII_PENDPRI 0x18 /* highest Pending Interrupt */
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/*
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* Interrupt Disctibutor (global)
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*/
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#define DIC_CONTROL 0x000
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#define DIC_CONTROL_ENABLE __BIT(0)
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#define DIC_TYPE 0x004
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#define DIC_TYPE_NCPUS_SHIFT 5
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#define DIC_TYPE_NCPUS_MASK __BITS(DIC_TYPE_NCPUS_SHIFT,7)
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#define DIC_TYPE_NLINES_SHIFT 0
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#define DIC_TYPE_NLINES_MASK __BITS(DIC_TYPE_NLINES_SHIFT,4)
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#define DIC_ENSET(n) (0x100 + (n)*sizeof (uint32_t)) /* n: 0..7 */
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#define DIC_ENCLEAR(n) (0x180 + (n)*sizeof (uint32_t))
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#define DIC_PENDSET(n) (0x200 + (n)*sizeof (uint32_t))
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#define DIC_PENDCLEAR(n) (0x280 + (n)*sizeof (uint32_t))
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#define DIC_ACTIVE(n) (0x300 + (n)*sizeof (uint32_t))
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#define DIC_PRIORITY(n) (0x400 + (n)*sizeof (uint32_t)) /* n: 0..63 */
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#define DIC_TARGET(n) (0x800 + (n)*sizeof (uint32_t))
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#define DIC_CONFIG(n) (0xc00 + (n)*sizeof (uint32_t)) /* n: 0..15 */
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#define DIC_LINELEVEL(n) (0xd00 + (n)*sizeof (uint32_t))
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#define DIC_SOFTINT 0xf00
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#endif /* _ARM_MPCORE_DICREG_H */
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