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93 lines
4.1 KiB
C
93 lines
4.1 KiB
C
/* $NetBSD: omap3_sdmmcreg.h,v 1.7 2013/07/27 17:10:28 jklos Exp $ */
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/*-
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_OMAP_OMAP3_SDMMCREG_H_
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#define _ARM_OMAP_OMAP3_SDMMCREG_H_
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#define SDMMC1_BASE_3430 0x4809C000
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#define SDMMC2_BASE_3430 0x480B4000
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#define SDMMC3_BASE_3430 0x480AD000
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#define SDMMC1_BASE_3530 0x4809C000
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#define SDMMC2_BASE_3530 0x480B4000
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#define SDMMC3_BASE_3530 0x480AD000
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#define SDMMC1_BASE_4430 0x4809C000 // same for omap5
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#define SDMMC2_BASE_4430 0x480B4000 // same for omap5
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#define SDMMC3_BASE_4430 0x480AD000 // same for omap5
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#define SDMMC4_BASE_4430 0x480D1000 // same for omap5
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#define SDMMC5_BASE_4430 0x480D5000 // same for omap5
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#define SDMMC1_BASE_TIAM335X 0x48060100
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#define SDMMC2_BASE_TIAM335X 0x481d8100
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#define SDMMC3_BASE_TIAM335X 0x47810100
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#define OMAP3_SDMMC_SDHC_OFFSET 0x100
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#define OMAP3_SDMMC_SDHC_SIZE 0x100
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#define MMCHS_SYSCONFIG 0x010 /* System Configuration */
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# define SYSCONFIG_CLOCKACTIVITY_MASK (3 << 8)
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# define SYSCONFIG_CLOCKACTIVITY_FCLK (2 << 8)
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# define SYSCONFIG_CLOCKACTIVITY_ICLK (1 << 8)
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# define SYSCONFIG_SIDLEMODE_MASK (3 << 3)
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# define SYSCONFIG_SIDLEMODE_AUTO (2 << 3)
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# define SYSCONFIG_ENAWAKEUP (1 << 2)
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# define SYSCONFIG_SOFTRESET (1 << 1)
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# define SYSCONFIG_AUTOIDLE (1 << 0)
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#define MMCHS_SYSSTATUS 0x014 /* System Status */
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# define SYSSTATUS_RESETDONE (1 << 0)
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#define MMCHS_CSRE 0x024 /* Card status response error */
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#define MMCHS_SYSTEST 0x028 /* System Test */
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#define MMCHS_CON 0x02c /* Configuration */
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# define CON_CLKEXTFREE (1 << 16)
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# define CON_PADEN (1 << 15) /* Ctrl Pow for MMC */
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# define CON_OBIE (1 << 14) /* Out-of-Band Intr */
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# define CON_OBIP (1 << 13) /*O-of-B Intr Polarity*/
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# define CON_CEATA (1 << 12) /* CE-ATA */
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# define CON_CTPL (1 << 11) /* Ctrl Power dat[1] */
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# define CON_DVAL_33US (0 << 9) /* debounce filter val*/
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# define CON_DVAL_231US (1 << 9) /* debounce filter val*/
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# define CON_DVAL_1MS (2 << 9) /* debounce filter val*/
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# define CON_DVAL_8_4MS (3 << 9) /* 8.4ms */
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# define CON_WPP (1 << 8) /* Write protect pol */
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# define CON_CDP (1 << 7) /*Card detect polarity*/
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# define CON_MIT (1 << 6) /* MMC interrupt cmd */
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# define CON_DW8 (1 << 5) /* 8-bit mode */
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# define CON_MODE (1 << 4) /* SYSTEST mode */
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# define CON_STR (1 << 3) /* Stream command */
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# define CON_HR (1 << 2) /* Broadcast host rsp */
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# define CON_INIT (1 << 1) /* Send init stream */
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# define CON_OD (1 << 0) /* Card open drain */
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#define MMCHS_PWCNT 0x030 /* Power counter */
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#define MMCHS_SYSCTL 0x12c /* SD system control register */
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# define SYSCTL_CEN (1 << 2) /* Clock enable */
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#endif
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