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101 lines
4.1 KiB
C
101 lines
4.1 KiB
C
/* $NetBSD: omap3_uhhreg.h,v 1.3 2014/03/29 23:32:41 matt Exp $ */
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/*-
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* Copyright (c) 2010 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _OMAP3_UHHREG_H
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#define _OMAP3_UHHREG_H
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/* 32-bit */
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#define UHH_REVISION 0x00
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#define UHH_REVISION_MAJOR(x) (((x) >> 4) & 0xf)
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#define UHH_REVISION_MINOR(x) ((x) & 0xf)
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#define UHH_REVISION_VERS2 2
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#define UHH_HWINFO 0x04
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#define UHH_HWINFO_SAR_CNTX_SIZE __BITS(9,0)
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#define UHH_SYSCONFIG 0x10
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#define UHH3_SYSCONFIG_MIDLEMODE_MASK 0x00003000
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#define UHH3_SYSCONFIG_MIDLEMODE_SMARTSTANDBY 0x00002000
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#define UHH3_SYSCONFIG_CLOCKACTIVITY 0x00000100
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#define UHH3_SYSCONFIG_SIDLEMODE_MASK 0x00000018
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#define UHH3_SYSCONFIG_SIDLEMODE_SMARTIDLE 0x00000008
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#define UHH3_SYSCONFIG_ENAWAKEUP 0x00000004
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#define UHH3_SYSCONFIG_SOFTRESET 0x00000002
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#define UHH3_SYSCONFIG_AUTOIDLE 0x00000001
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#define UHH4_SYSCONFIG_STANDBYMODE __BITS(5,4)
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#define UHH4_SYSCONFIG_STANDBYMODE_SMARTSTANDBY __SHIFTIN(2,UHH4_SYSCONFIG_STANDBYMODE)
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#define UHH4_SYSCONFIG_SIDLEMODE __BITS(3,2)
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#define UHH4_SYSCONFIG_SIDLEMODE_SMARTIDLE __SHIFTIN(2,UHH4_SYSCONFIG_SIDLEMODE)
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#define UHH4_SYSCONFIG_SOFTRESET __BIT(0)
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#define UHH_SYSSTATUS 0x14
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#define UHH_SYSSTATUS_EHCI_RESETDONE 0x00000004
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#define UHH_SYSSTATUS_OHCI_RESETDONE 0x00000002
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#define UHH3_SYSSTATUS_RESETDONE 0x00000001
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#define UHH3_SYSSTATUS_RESETDONE_ALL \
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(UHH_SYSSTATUS_EHCI_RESETDONE | \
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UHH_SYSSTATUS_OHCI_RESETDONE | \
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UHH3_SYSSTATUS_RESETDONE)
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#define UHH4_SYSSTATUS_RESETDONE_ALL \
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(UHH_SYSSTATUS_EHCI_RESETDONE | \
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UHH_SYSSTATUS_OHCI_RESETDONE)
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#define UHH_HOSTCONFIG 0x40
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#define UHH_HOSTCONFIG_APP_START_CLK __BIT(31)
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#define UHH_HOSTCONFIG_P3_MODE __BITS(21,20)
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#define UHH_HOSTCONFIG_P2_MODE __BITS(19,18)
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#define UHH_HOSTCONFIG_P1_MODE __BITS(17,16)
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#define UHH_HOSTCONFIG_PMODE_ULPI_PHY 0
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#define UHH_HOSTCONFIG_PMODE_UTMI 1
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#define UHH_HOSTCONFIG_PMODE__RSVD2 2
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#define UHH_HOSTCONFIG_PMODE_HSIC 3
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#define UHH_HOSTCONFIG_P3_ULPI_BYPASS __BIT(12)
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#define UHH_HOSTCONFIG_P2_ULPI_BYPASS __BIT(11)
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#define UHH_HOSTCONFIG_P3_CONNECT_STATUS __BIT(10)
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#define UHH_HOSTCONFIG_P2_CONNECT_STATUS __BIT(9)
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#define UHH_HOSTCONFIG_P1_CONNECT_STATUS __BIT(8)
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#define UHH_HOSTCONFIG_ENA_INCR_ALIGN __BIT(5)
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#define UHH_HOSTCONFIG_ENA_INCR16 __BIT(4)
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#define UHH_HOSTCONFIG_ENA_INCR8 __BIT(3)
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#define UHH_HOSTCONFIG_ENA_INCR4 __BIT(2)
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#define UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN __BIT(1)
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#define UHH_HOSTCONFIG_P1_ULPI_BYPASS __BIT(0)
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#define UHH_DEBUG_CSR 0x44
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#define UHH_DEBUG_CSR_OHCI_CCS_3 0x00080000
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#define UHH_DEBUG_CSR_OHCI_CCS_2 0x00040000
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#define UHH_DEBUG_CSR_OHCI_CCS_1 0x00020000
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#define UHH_DEBUG_CSR_OHCI_GLOBALSUSPEND 0x00010000
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#define UHH_DEBUG_CSR_OHCI_CNTSEL 0x00000080
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#define UHH_DEBUG_CSR_EHCI_SIMULATION_MODE 0x00000040
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#define UHH_DEBUG_CSR_EHCI_FLADJ 0x0000003f
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#define UHH_SAR_CNTX_BASE 0x100
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#endif /* !_OMAP3_UHHREG_H */
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