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255 lines
10 KiB
C
255 lines
10 KiB
C
/* $NetBSD: exynos5_loc.c,v 1.12 2014/09/05 08:01:05 skrll Exp $ */
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/*-
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* Copyright (c) 2014 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Nick Hudson
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arm/samsung/exynos_io.h>
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#include <arm/samsung/exynos_intr.h>
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#include <arm/samsung/exynos5_reg.h>
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#define IRQ_RP_TIMER IRQ_SPI(127)
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#define IRQ_CAM_B IRQ_SPI(126)
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#define IRQ_CAM_A IRQ_SPI(125)
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#define IRQ_MDMA1 IRQ_SPI(124)
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#define IRQ_MCT_L1 IRQ_SPI(121)
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#define IRQ_MCT_L0 IRQ_SPI(120)
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#define IRQ_G3D_IRQMMU IRQ_SPI(119)
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#define IRQ_G3D_IRQJOB IRQ_SPI(118)
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#define IRQ_G3D_IRQGPU IRQ_SPI(117)
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#define IRQ_SATA IRQ_SPI(115)
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#define IRQ_CEC IRQ_SPI(114)
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#define IRQ_DP1_1 IRQ_SPI(113)
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#define IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
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#define IRQ_PMU IRQ_SPI(111)
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#define IRQ_CAM_C IRQ_SPI(110)
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#define IRQ_SATAPMEREQ IRQ_SPI(109)
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#define IRQ_SATAPHY IRQ_SPI(108)
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#define IRQ_ADC0 IRQ_SPI(106)
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#define IRQ_SPDIF IRQ_SPI(105)
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#define IRQ_PCM2 IRQ_SPI(104)
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#define IRQ_PCM1 IRQ_SPI(103)
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#define IRQ_PCM0 IRQ_SPI(102)
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#define IRQ_AC97 IRQ_SPI(101)
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#define IRQ_I2S2 IRQ_SPI(100)
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#define IRQ_I2S1 IRQ_SPI(99)
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#define IRQ_I2S0 IRQ_SPI(98)
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#define IRQ_AUDIO_SS IRQ_SPI(97)
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#define IRQ_MFC IRQ_SPI(96)
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#define IRQ_HDMI IRQ_SPI(95)
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#define IRQ_MIXER IRQ_SPI(94)
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#define IRQ_EFNFCON_1 IRQ_SPI(93)
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#define IRQ_EFNFCON_0 IRQ_SPI(92)
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#define IRQ_G2D IRQ_SPI(91)
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#define IRQ_EFNFCON_DMA IRQ_SPI(90)
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#define IRQ_JPEG IRQ_SPI(89)
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#define IRQ_GSCL3 IRQ_SPI(88)
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#define IRQ_GSCL2 IRQ_SPI(87)
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#define IRQ_GSCL1 IRQ_SPI(86)
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#define IRQ_GSCL0 IRQ_SPI(85)
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#define IRQ_ROTATOR IRQ_SPI(84)
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#define IRQ_WDT_IOP IRQ_SPI(83)
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#define IRQ_MIPI_DSI_4LANE IRQ_SPI(82)
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#define IRQ_EFNFCON_DMA_ABORT IRQ_SPI(81)
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#define IRQ_MIPI_CSI_B IRQ_SPI(80)
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#define IRQ_MIPI_CSI_A IRQ_SPI(79)
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#define IRQ_SDMMC3 IRQ_SPI(78)
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#define IRQ_SDMMC2 IRQ_SPI(77)
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#define IRQ_SDMMC1 IRQ_SPI(76)
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#define IRQ_SDMMC0 IRQ_SPI(75)
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#define IRQ_USBOTG IRQ_SPI(74)
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#define IRQ_MIPI_HSI IRQ_SPI(73)
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#define IRQ_USB_DRD30 IRQ_SPI(72)
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#define IRQ_USB_HOST20 IRQ_SPI(71)
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#define IRQ_SPI2 IRQ_SPI(70)
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#define IRQ_SPI1 IRQ_SPI(69)
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#define IRQ_SPI0 IRQ_SPI(68)
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#define IRQ_CPU_NFIQ_1 IRQ_SPI(67)
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#define IRQ_CPU_NFIQ_0 IRQ_SPI(66)
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#define IRQ_TMU IRQ_SPI(65)
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#define IRQ_HDMI_I2C IRQ_SPI(64)
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#define IRQ_I2C7 IRQ_SPI(63)
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#define IRQ_I2C6 IRQ_SPI(62)
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#define IRQ_I2C5 IRQ_SPI(61)
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#define IRQ_I2C4 IRQ_SPI(60)
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#define IRQ_I2C3_USI3 IRQ_SPI(59)
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#define IRQ_I2C2_USI2 IRQ_SPI(58)
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#define IRQ_I2C1_USI1 IRQ_SPI(57)
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#define IRQ_I2C0_USI0 IRQ_SPI(56)
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#define IRQ_MONOCNT IRQ_SPI(55)
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#define IRQ_UART3 IRQ_SPI(54)
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#define IRQ_UART2 IRQ_SPI(53)
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#define IRQ_UART1 IRQ_SPI(52)
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#define IRQ_UART0 IRQ_SPI(51)
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#define IRQ_GPIO_C2C IRQ_SPI(50)
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#define IRQ_GPIO IRQ_SPI(47)
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#define IRQ_GPIO_LB IRQ_SPI(46)
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#define IRQ_GPIO_RT IRQ_SPI(45)
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#define IRQ_RTC_TIC IRQ_SPI(44)
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#define IRQ_RTC_ALARM IRQ_SPI(43)
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#define IRQ_WDT IRQ_SPI(42)
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#define IRQ_RTIC IRQ_SPI(41)
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#define IRQ_TIMER4 IRQ_SPI(40)
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#define IRQ_TIMER3 IRQ_SPI(39)
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#define IRQ_TIMER2 IRQ_SPI(38)
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#define IRQ_TIMER1 IRQ_SPI(37)
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#define IRQ_TIMER0 IRQ_SPI(36)
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#define IRQ_PDMA1 IRQ_SPI(35)
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#define IRQ_PDMA0 IRQ_SPI(34)
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#define IRQ_MDMA0_CORE IRQ_SPI(33)
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#define IRQ_SYSMMU_DRCISP_1 EXYNOS_COMBINERIRQ(11, 7)
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#define IRQ_SYSMMU_ODC_1 EXYNOS_COMBINERIRQ(11, 1)
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#define IRQ_SYSMMU_ODC_0 EXYNOS_COMBINERIRQ(11, 0)
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#define IRQ_SYSMMU_ISP_1 EXYNOS_COMBINERIRQ(10, 7)
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#define IRQ_SYSMMU_ISP_0 EXYNOS_COMBINERIRQ(10, 6)
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#define IRQ_SYSMMU_DIS0_1 EXYNOS_COMBINERIRQ(10, 5)
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#define IRQ_SYSMMU_DIS0_0 EXYNOS_COMBINERIRQ(10, 4)
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#define IRQ_DP1 EXYNOS_COMBINERIRQ(10, 3)
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#define IRQ_SYSMMU_DIS1_1 EXYNOS_COMBINERIRQ(9, 5)
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#define IRQ_SYSMMU_DIS1_0 EXYNOS_COMBINERIRQ(9, 4)
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#define IRQ_SYSMMU_MFCL_1 EXYNOS_COMBINERIRQ(8, 6)
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#define IRQ_SYSMMU_MFCL_0 EXYNOS_COMBINERIRQ(8, 5)
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#define IRQ_SYSMMU_TV_M0_1 EXYNOS_COMBINERIRQ(7, 5)
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#define IRQ_SYSMMU_TV_M0_0 EXYNOS_COMBINERIRQ(7, 4)
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#define IRQ_SYSMMU_MDMA1_1 EXYNOS_COMBINERIRQ(7, 3)
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#define IRQ_SYSMMU_MDMA1_0 EXYNOS_COMBINERIRQ(7, 2)
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#define IRQ_SYSMMU_MDMA0_1 EXYNOS_COMBINERIRQ(7, 1)
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#define IRQ_SYSMMU_MDMA0_0 EXYNOS_COMBINERIRQ(7, 0)
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#define IRQ_SYSMMU_SSS_1 EXYNOS_COMBINERIRQ(6, 7)
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#define IRQ_SYSMMU_SSS_0 EXYNOS_COMBINERIRQ(6, 6)
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#define IRQ_SYSMMU_RTIC_1 EXYNOS_COMBINERIRQ(6, 5)
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#define IRQ_SYSMMU_RTIC_0 EXYNOS_COMBINERIRQ(6, 4)
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#define IRQ_SYSMMU_MFCR_1 EXYNOS_COMBINERIRQ(6, 3)
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#define IRQ_SYSMMU_MFCR_0 EXYNOS_COMBINERIRQ(6, 2)
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#define IRQ_SYSMMU_ARM_1 EXYNOS_COMBINERIRQ(6, 1)
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#define IRQ_SYSMMU_ARM_0 EXYNOS_COMBINERIRQ(5, 0)
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#define IRQ_SYSMMU_3DNR_1 EXYNOS_COMBINERIRQ(5, 7)
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#define IRQ_SYSMMU_3DNR_0 EXYNOS_COMBINERIRQ(5, 6)
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#define IRQ_SYSMMU_MCUISP_1 EXYNOS_COMBINERIRQ(5, 5)
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#define IRQ_SYSMMU_MCUISP_0 EXYNOS_COMBINERIRQ(5, 4)
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#define IRQ_SYSMMU_SCALERCISP_1 EXYNOS_COMBINERIRQ(5, 3)
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#define IRQ_SYSMMU_SCALERCISP_0 EXYNOS_COMBINERIRQ(5, 2)
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#define IRQ_SYSMMU_FDISP_1 EXYNOS_COMBINERIRQ(5, 1)
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#define IRQ_SYSMMU_FDISP_0 EXYNOS_COMBINERIRQ(5, 0)
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#define IRQ_MCUIOP_CTIIRQ EXYNOS_COMBINERIRQ(4, 7)
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#define IRQ_MCUIOP_PMUIRQ EXYNOS_COMBINERIRQ(4, 6)
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#define IRQ_MCUISP_CTIIRQ EXYNOS_COMBINERIRQ(4, 5)
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#define IRQ_MCUISP_PMUIRQ EXYNOS_COMBINERIRQ(4, 4)
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#define IRQ_SYSMMU_JPEGX_1 EXYNOS_COMBINERIRQ(4, 3)
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#define IRQ_SYSMMU_JPEGX_0 EXYNOS_COMBINERIRQ(4, 2)
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#define IRQ_SYSMMU_ROTATOR_1 EXYNOS_COMBINERIRQ(4, 1)
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#define IRQ_SYSMMU_ROTATOR_0 EXYNOS_COMBINERIRQ(4, 0)
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#define IRQ_SYSMMU_SCALERPISP_1 EXYNOS_COMBINERIRQ(3, 7)
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#define IRQ_SYSMMU_SCALERPISP_0 EXYNOS_COMBINERIRQ(3, 6)
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#define IRQ_SYSMMU_FIMC_LITE0_1 EXYNOS_COMBINERIRQ(3, 5)
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#define IRQ_SYSMMU_FIMC_LITE0_0 EXYNOS_COMBINERIRQ(3, 4)
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#define IRQ_SYSMMU_DISP1_M0_1 EXYNOS_COMBINERIRQ(3, 3)
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#define IRQ_SYSMMU_DISP1_M0_0 EXYNOS_COMBINERIRQ(3, 2)
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#define IRQ_SYSMMU_FIMC_LITE2_1 EXYNOS_COMBINERIRQ(3, 1)
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#define IRQ_SYSMMU_FIMC_LITE2_0 EXYNOS_COMBINERIRQ(3, 0)
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#define IRQ_SYSMMU_GSCL3_1 EXYNOS_COMBINERIRQ(2, 7)
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#define IRQ_SYSMMU_GSCL3_0 EXYNOS_COMBINERIRQ(2, 6)
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#define IRQ_SYSMMU_GSCL2_1 EXYNOS_COMBINERIRQ(2, 5)
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#define IRQ_SYSMMU_GSCL2_0 EXYNOS_COMBINERIRQ(2, 4)
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#define IRQ_SYSMMU_GSCL1_1 EXYNOS_COMBINERIRQ(2, 3)
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#define IRQ_SYSMMU_GSCL1_0 EXYNOS_COMBINERIRQ(2, 2)
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#define IRQ_SYSMMU_GSCL0_1 EXYNOS_COMBINERIRQ(2, 1)
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#define IRQ_SYSMMU_GSCL0_0 EXYNOS_COMBINERIRQ(2, 0)
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#define IRQ_CPU_NCNTVIRQ_0 EXYNOS_COMBINERIRQ(1, 7)
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#define IRQ_CPU_NCNTPSIRQ_0 EXYNOS_COMBINERIRQ(1, 6)
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#define IRQ_CPU_NCNTPSNIRQ_0 EXYNOS_COMBINERIRQ(1, 5)
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#define IRQ_CPU_NCNTHPIRQ_0 EXYNOS_COMBINERIRQ(1, 4)
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#define IRQ_CPU_NCTIIRQ_0 EXYNOS_COMBINERIRQ(1, 3)
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#define IRQ_CPU_NPMUIRQ_0 EXYNOS_COMBINERIRQ(1, 2)
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#define IRQ_CPU_PARITYFAILSCU_0 EXYNOS_COMBINERIRQ(1, 1)
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#define IRQ_CPU_PARITYFAIL0 EXYNOS_COMBINERIRQ(1, 0)
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#define IRQ_TZASC_XR1BXW EXYNOS_COMBINERIRQ(0, 7)
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#define IRQ_TZASC_XR1BXR EXYNOS_COMBINERIRQ(0, 6)
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#define IRQ_TZASC_XLBXW EXYNOS_COMBINERIRQ(0, 5)
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#define IRQ_TZASC_XLBXR EXYNOS_COMBINERIRQ(0, 4)
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#define IRQ_TZASC_DRBXW EXYNOS_COMBINERIRQ(0, 3)
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#define IRQ_TZASC_DRBXR EXYNOS_COMBINERIRQ(0, 2)
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#define IRQ_TZASC_CBXW EXYNOS_COMBINERIRQ(0, 1)
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#define IRQ_TZASC_CBXR EXYNOS_COMBINERIRQ(0, 0)
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#define OFFANDSIZE(p,n) \
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EXYNOS5##p##_##n##_OFFSET, 0x10000
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static const struct exyo_locators exynos5_locators[] = {
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{ "exyogpio", 0, 0, NOPORT, NOINTR, 0 },
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{ "exyoiic", 0, 0, NOPORT, NOINTR, 0 },
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{ "exyowdt", OFFANDSIZE(,WDT), NOPORT, IRQ_WDT, 0 },
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{ "sscom", OFFANDSIZE(,UART0), 0, IRQ_UART0, 0 },
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{ "sscom", OFFANDSIZE(,UART1), 1, IRQ_UART1, 0 },
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{ "sscom", OFFANDSIZE(,UART2), 2, IRQ_UART2, 0 },
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{ "sscom", OFFANDSIZE(,UART3), 3, IRQ_UART3, 0 },
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{ "exyousb", OFFANDSIZE(,USB2HOST), NOPORT, IRQ_USB_HOST20, 0 },
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};
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const struct exyo_locinfo exynos5_locinfo = {
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.locators = exynos5_locators,
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.nlocators = __arraycount(exynos5_locators)
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};
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/* flag signal the use of gpio */
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static const struct exyo_locators exynos5_i2c_locators[] = {
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/* busname, sdabit, slcbit, func */
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{ "iic0", OFFANDSIZE(,I2C0), 0, IRQ_I2C0_USI0, 1 , "GPB3", 0, 1, 2 },
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{ "iic1", OFFANDSIZE(,I2C1), 1, IRQ_I2C1_USI1, 1 , "GPB3", 2, 3, 2 },
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{ "iic2", OFFANDSIZE(,I2C2), 2, IRQ_I2C2_USI2, 1 , "GPA0", 6, 7, 3 },
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{ "iic3", OFFANDSIZE(,I2C3), 3, IRQ_I2C3_USI3, 1 , "GPA1", 2, 3, 3 },
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{ "iic4", OFFANDSIZE(,I2C4), 4, IRQ_I2C4, 1 , "GPA2", 0, 1, 3 },
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{ "iic5", OFFANDSIZE(,I2C5), 5, IRQ_I2C5, 1 , "GPA2", 2, 3, 3 },
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{ "iic6", OFFANDSIZE(,I2C6), 6, IRQ_I2C6, 1 , "GPB1", 3, 4, 4 },
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{ "iic7", OFFANDSIZE(,I2C7), 7, IRQ_I2C7, 1 , "GPB2", 2, 3, 3 },
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{ "iic8", OFFANDSIZE(,I2CHDMI), 8, IRQ_HDMI_I2C, 0 , "", 0, 0, 0 },
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};
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const struct exyo_locinfo exynos5_i2c_locinfo = {
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.locators = exynos5_i2c_locators,
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.nlocators = __arraycount(exynos5_i2c_locators)
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};
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