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81 lines
3.2 KiB
C
81 lines
3.2 KiB
C
/* $NetBSD: mct_reg.h,v 1.2 2014/09/05 08:01:05 skrll Exp $ */
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/*-
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* Copyright (c) 2014 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Reinoud Zandijk.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_SAMSUNG_MCT_REG_H_
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#define _ARM_SAMSUNG_MCT_REG_H_
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/* global timer register offsets */
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#define MCT_G_CNT_L 0x100 /* lower bits */
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#define MCT_G_CNT_U 0x104 /* higher bits */
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#define MCT_G_CNT_WSTAT 0x110 /* wait for write OK cntr */
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#define G_CNT_WSTAT_L __BIT(0)
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#define G_CNT_WSTAT_U __BIT(1)
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#define MCT_G_COMP0_L 0x200 /* compare0 lower bits */
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#define MCT_G_COMP0_U 0x204 /* compare0 higher bits */
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#define MCT_G_COMP0_ADD_INCR 0x208 /* compare0 auto add value */
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#define MCT_G_TCON 0x240 /* configuration register */
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#define G_TCON_COMP0_ENABLE __BIT(0)
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#define G_TCON_COMP0_AUTOINC __BIT(1)
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#define G_TCON_START __BIT(8)
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#define MCT_G_INT_CSTAT 0x244 /* clear interrupt */
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#define G_INT_CSTAT_CLEAR __BIT(0)
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#define MCT_G_INT_ENB 0x248 /* enable interrupts */
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#define G_INT_ENB_ENABLE __BIT(0)
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#define MCT_G_WSTAT 0x24C /* wait for write OK */
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#define G_WSTAT_COMP0_L __BIT(0)
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#define G_WSTAT_COMP0_U __BIT(1)
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#define G_WSTAT_ADD_INCR __BIT(2)
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#define G_WSTAT_TCON __BIT(16)
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/* local cpu-bound timers */
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#define MCT_L_OFFSET(x) (0x300 + (0x100 * x))
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#define MCT_L_MASK 0xffffff00
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#define MCT_L_TCNTB 0x00 /* TODO: what */
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#define MCT_L_ICNTB 0x08 /* interrupt count buffer */
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#define L_INCTB_UPDATE(x) (__BIT(31) | (x))
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#define MCT_L_TCON 0x20 /* configuration register */
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#define L_TCON_TIMER_START __BIT(0)
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#define L_TCON_INT_START __BIT(1)
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#define L_TCON_INTERVAL_MODE __BIT(2)
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#define MCT_L_INC_CSTAT 0x30
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#define L_INC_CSTAT_CLEAR __BIT(0)
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#define MCT_L_INT_ENB 0x34
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#define L_INT_ENB_ENABLE __BIT(0)
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#define MCT_L_WSTAT 0x40
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#define L_WSTAT_L_TCNTB __BIT(0)
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#define L_WSTAT_L_ICNTB __BIT(1)
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#define L_WSTAT_L_TCON __BIT(3)
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#endif /* _ARM_SAMSUNG_MCT_REG_H_ */
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