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104 lines
3.1 KiB
C
104 lines
3.1 KiB
C
/* $NetBSD: zynq7000_intr.h,v 1.1 2015/01/23 12:34:09 hkenken Exp $ */
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/*-
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* Copyright (c) 2015 Genetec Corporation. All rights reserved.
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* Written by Hashimoto Kenichi for Genetec Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_ZYNQ_ZYNQ7000_INTR_H_
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#define _ARM_ZYNQ_ZYNQ7000_INTR_H_
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#define PIC_MAXSOURCES 128
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#define PIC_MAXMAXSOURCES 128
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/*
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* The ZYNQ7000 uses a generic interrupt controller so pull that stuff.
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*/
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#include <arm/cortex/gic_intr.h>
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#include <arm/cortex/a9tmr_intr.h> /* A9 Timer PPIs */
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#define IRQ_CPU0 32
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#define IRQ_CPU1 33
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#define IRQ_L2CC 34
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#define IRQ_OCM 35
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#define IRQ__RSVD36 36
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#define IRQ_PMU0 37
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#define IRQ_PMU1 38
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#define IRQ_XADC 39
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#define IRQ_DVI 40
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#define IRQ_SWDT 41
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#define IRQ_TTC0 42
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#define IRQ__RSVD44 44
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#define IRQ_DMAC_ABORT 45
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#define IRQ_DMAC0 46
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#define IRQ_DMAC1 47
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#define IRQ_DMAC2 48
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#define IRQ_DMAC3 49
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#define IRQ_SMC 50
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#define IRQ_QSPI 51
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#define IRQ_GPIO 52
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#define IRQ_USB0 53
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#define IRQ_ETH0 54
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#define IRQ_ETH0_WU 55
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#define IRQ_SDIO0 56
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#define IRQ_I2C0 57
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#define IRQ_SPI0 58
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#define IRQ_UART0 59
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#define IRQ_CAN0 60
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#define IRQ_FPGA0 60
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#define IRQ_FPGA1 61
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#define IRQ_FPGA2 62
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#define IRQ_FPGA3 64
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#define IRQ_FPGA4 65
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#define IRQ_FPGA5 66
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#define IRQ_FPGA6 67
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#define IRQ_FPGA7 68
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#define IRQ_TTC1 69
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#define IRQ_DMAC4 72
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#define IRQ_DMAC5 73
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#define IRQ_DMAC6 74
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#define IRQ_DMAC7 75
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#define IRQ_USB1 76
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#define IRQ_ETH1 77
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#define IRQ_ETH1_WU 78
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#define IRQ_SDIO1 79
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#define IRQ_I2C1 80
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#define IRQ_SPI1 81
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#define IRQ_UART1 82
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#define IRQ_CAN1 83
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#define IRQ_FPGA8 84
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#define IRQ_FPGA9 85
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#define IRQ_FPGA10 86
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#define IRQ_FPGA11 87
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#define IRQ_FPGA12 88
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#define IRQ_FPGA13 89
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#define IRQ_FPGA14 90
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#define IRQ_FPGA15 91
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#define IRQ_PARITY 92
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#define IRQ__RSVD93 93
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#define IRQ__RSVD94 94
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#define IRQ__RSVD95 95
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#endif /* _ARM_ZYNQ_ZYNQ7000_INTR_H_ */
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