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58 lines
2.2 KiB
C
58 lines
2.2 KiB
C
/* $NetBSD: zynq7000_reg.h,v 1.1 2015/01/23 12:34:09 hkenken Exp $ */
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/*-
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* Copyright (c) 2015 Genetec Corporation. All rights reserved.
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* Written by Hashimoto Kenichi for Genetec Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_ZYNQ_ZYNQ7000_REG_H_
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#define _ARM_ZYNQ_ZYNQ7000_REG_H_
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#define ZYNQ7000_IOREG_PBASE 0xe0000000
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#define ZYNQ7000_IOREG_SIZE 0x00200000
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#define ZYNQ7000_ARMCORE_PBASE 0xf8f00000
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#define ZYNQ7000_ARMCORE_SIZE 0x00100000
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#define ZYNQ7000_IO_SIZE (ZYNQ7000_IOREG_SIZE + ZYNQ7000_ARMCORE_SIZE)
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#define SLCR_BASE 0xf8000000
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#define SLCR_SIZE 0x00000b78
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#define UART0_BASE 0xe0000000
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#define UART1_BASE 0xe0001000
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#define UART_SIZE 0x00000048
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#define ARMCORE_SCU_BASE 0x00000000
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#define ARMCORE_L2C_BASE 0x00002000
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#define USB0_BASE 0xe0002000
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#define USB1_BASE 0xe0003000
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#define USB_SIZE 0x00000200
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#define SDIO0_BASE 0xe0100000
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#define SDIO1_BASE 0xe0101000
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#define SDIO_SIZE 0x00001000
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#endif /* _ARM_ZYNQ_ZYNQ7000_REG_H_ */
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