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100 lines
3.3 KiB
C
100 lines
3.3 KiB
C
/* $NetBSD: zynq7000_var.h,v 1.1 2015/01/23 12:34:09 hkenken Exp $ */
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/*-
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* Copyright (c) 2015 Genetec Corporation. All rights reserved.
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* Written by Hashimoto Kenichi for Genetec Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_ZYNQ_ZYNQ7000_VAR_H_
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#define _ARM_ZYNQ_ZYNQ7000_VAR_H_
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#include <sys/bus.h>
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#include <sys/cpu.h>
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struct axi_attach_args {
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const char *aa_name;
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bus_space_tag_t aa_iot;
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bus_dma_tag_t aa_dmat;
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bus_addr_t aa_addr;
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bus_size_t aa_size;
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int aa_irq;
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int aa_irqbase;
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};
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struct zynq7000_clock_info {
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uint32_t clk_ps; /* Reference */
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uint32_t clk_arm_base;
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uint32_t clk_ddr_base;
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uint32_t clk_io_base;
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uint32_t clk_cpu_6x4x; /* ARM PLL */
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uint32_t clk_cpu_3x2x; /* ARM PLL */
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uint32_t clk_cpu_2x; /* ARM PLL */
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uint32_t clk_cpu_1x; /* ARM PLL */
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uint32_t clk_ddr_3x; /* DDR PLL */
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uint32_t clk_ddr_2x; /* DDR PLL */
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uint32_t clk_ddr_dci; /* DDR PLL */
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uint32_t clk_smc; /* IO PLL */
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uint32_t clk_qspi; /* IO PLL */
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uint32_t clk_gige0; /* IO PLL */
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uint32_t clk_gige1; /* IO PLL */
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uint32_t clk_sdio; /* IO PLL */
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uint32_t clk_uart; /* IO PLL */
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uint32_t clk_spi; /* IO PLL */
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uint32_t clk_can; /* IO PLL */
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uint32_t clk_pcap; /* IO PLL */
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uint32_t clk_dbg; /* IO PLL */
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uint32_t clk_fclk0; /* IO PLL */
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uint32_t clk_fclk1; /* IO PLL */
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uint32_t clk_fclk2; /* IO PLL */
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uint32_t clk_fclk3; /* IO PLL */
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};
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struct cpu_softc {
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struct cpu_info *cpu_ci;
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bus_space_tag_t cpu_ioreg_bst;
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bus_space_tag_t cpu_armcore_bst;
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bus_space_handle_t cpu_ioreg_bsh;
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bus_space_handle_t cpu_armcore_bsh;
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struct zynq7000_clock_info cpu_clk;
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};
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/* Clock */
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#define ZYNQ7000_PS_CLK (33333333) /* 33.333 MHz */
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#ifdef _KERNEL
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void zynq7000_bootstrap(vaddr_t);
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psize_t zynq7000_memprobe(void);
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void zynq7000_device_register(device_t, void *);
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void zynq7000_cpu_hatch(struct cpu_info *);
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extern struct bus_space zynq_bs_tag;
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extern struct arm32_bus_dma_tag zynq_bus_dma_tag;
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extern struct zynq7000_clock_info clk_info;
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extern bus_space_tag_t zynq7000_armcore_bst;
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extern bus_space_handle_t zynq7000_armcore_bsh;
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#endif
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#endif /* _ARM_ZYNQ_ZYNQ7000_VAR_H_ */
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