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63 lines
1.9 KiB
C
63 lines
1.9 KiB
C
/* $NetBSD: zynq_slcrvar.h,v 1.1 2015/01/23 12:34:09 hkenken Exp $ */
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/*-
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* Copyright (c) 2015 Genetec Corporation. All rights reserved.
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* Written by Hashimoto Kenichi for Genetec Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_ZYNQ_ZYNQ_SLCRVAR_H
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#define _ARM_ZYNQ_ZYNQ_SLCRVAR_H
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enum zynq_clocks {
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CLK_PS,
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CLK_ARM_PLL,
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CLK_DDR_PLL,
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CLK_IO_PLL,
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CLK_CPU_6X4X,
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CLK_CPU_3X2X,
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CLK_CPU_2X,
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CLK_CPU_1X,
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CLK_DDR_3X,
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CLK_DDR_2X,
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CLK_DDR_DCI,
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CLK_SMC,
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CLK_QSPI,
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CLK_GIGE0,
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CLK_GIGE1,
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CLK_SDIO,
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CLK_UART,
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CLK_SPI,
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CLK_CAN,
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CLK_PCAP,
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CLK_DBG,
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CLK_FCLK0,
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CLK_FCLK1,
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CLK_FCLK2,
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CLK_FCLK3,
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CLK_MAX
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};
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uint32_t zynq_get_clock(enum zynq_clocks);
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#endif /* _ARM_ZYNQ_ZYNQ_SLCRVAR_H */
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